Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.

Wafer bonding apparatus and method are provided. A method includes performing a first plasma activation process on a first surface of a first wafer. The first plasma activation process forms a first high-activation region and a first low-activation region on the first surface of the first wafer. A first cleaning process is performed on the first surface of the first wafer. The first cleaning process forms a first plurality of silanol groups in the first high-activation region and the first low-activation region. The first high-activation region includes more silanol groups than the first low-activation region. The first wafer is bonded to a second wafer.

A semiconductor device that can be miniaturized or highly integrated is provided. The semiconductor device includes a transistor. The transistor includes an oxide, a first conductor and a second conductor that are over the oxide, a first insulator over the first conductor and the second conductor, a second insulator in an opening included in the first insulator, a third insulator over the second insulator, a fourth insulator over the third insulator, and a third conductor over the fourth insulator. The opening includes a region overlapping with the oxide. The third conductor includes a region overlapping with the oxide with the second insulator, the third insulator, and the fourth insulator therebetween. The second insulator is in contact with a top surface of the oxide and a sidewall of the opening. The thickness of the second insulator is smaller than that of the third insulator. The fourth insulator is less permeable to oxygen than the third insulator is. The third conductor has a width greater than or equal to 3 nm and less than or equal to 15 nm in a cross-sectional view of the transistor in the channel length direction.

A method of forming a contact to a semiconductor device that includes forming a vertically orientated channel region on semiconductor material layer of a substrate; and forming a first source/drain region in the semiconductor material layer. The method may continue with forming a metal semiconductor alloy contact on the first source/drain region extending along a horizontally orientated upper surface of the first source/drain region that is substantially perpendicular to the vertically orientated channel region, wherein the metal semiconductor alloy contact extends substantially to an interface with the vertically orientated channel region. Thereafter, a gate structure is formed on the vertically orientated channel region, and a second source/drain region is formed on the vertically orientated channel region.

A method of controlling formation of junctions in a lateral bipolar junction transistor comprises: providing a starting substrate comprising a bulk silicon material as a handle substrate, a buried oxide layer on the handle substrate, and an intrinsic base semiconductor layer of germanium on the buried oxide layer; forming an extrinsic base layer on the intrinsic base semiconductor layer; etching at least a portion of the base layer; disposing a sidewall spacer on a side of the base layer; disposing a faceted germanium layer adjacent the sidewall spacer; recessing the faceted germanium layer and the intrinsic base semiconductor layer below the sidewall spacer; using a hot angle ion implantation technique to implant ions into a side of the intrinsic base semiconductor layer to form a junction edge/profile; annealing the implanted ions; and epitaxially growing a Si or SiGe layer on the germanium layer and the junction edge/profile.

A process for making an integrated circuit, either in the form of a wafer, die, or chip, includes instantiating multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such instantiated fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such instantiated fill cells further include geometry to enable non-contact evaluation of Tip-to-Side shorts and/or leakages.

Embodiments of a method for generating ions in an ion source are provided. The method for generating ions in an ion source includes introducing a dopant gas and a diluent gas into an ion source arc chamber. The method for generating ions in an ion source further includes generating plasma in the ion source arc chamber based on the dopant gas and the diluent gas. In addition, the dopant gas includes carbon monoxide, and the diluent gas includes xenon and hydrogen.

A method of manufacturing p-n junction in semiconductor material such that small dimensions of such junctions are maintained, and associated lattice dislocations of such junctions may be preferentially maintained, and devices with such patterned semiconductor material, is disclosed. Typically, a neutron moderator is used to slow fast neutrons to thermal energies. A mask made from thermal neutron absorbing material, such as cadmium, is placed in close proximity to such neutron moderator. Thermal neutron focusing optics, such as compound refractive lenses, are used to collect and focus thermal neutrons emitted from the mask such that the pattern or portion of the pattern is transferred to the silicon body, with neutrons transmitted from the window areas in the mask and through the neutron optic so as to form the donor dopant concentration for the n-type regions by transmutation of silicon atoms into phosphorus. An electronic device produced by such a method has vertical p-n junctions continuous between both major surfaces and horizontal alternating p-type and n-type regions across most of the face of the material, such that unique properties are achieved.

Disclosed are a method for producing an oxide film using a low temperature process, an oxide film and an electronic device. The method for producing an oxide film according to an embodiment of the present invention includes the steps of coating a substrate with an oxide solution, and irradiating the oxide solution coat with ultraviolet rays under an inert gas atmosphere.

Disclosed are a method for producing an oxide film using a low temperature process, an oxide film and an electronic device. The method for producing an oxide film according to an embodiment of the present invention includes the steps of coating a substrate with an oxide solution, and irradiating the oxide solution coat with ultraviolet rays under an inert gas atmosphere.