Gate metal is removed from a region containing transistors such as nanosheet transistors or vertical transport field-effect transistors using techniques that control the undercutting of gate metal in an adjoining region. A dielectric spacer layer is deposited on the transistors. A first etch causes the removal of gate metal over the boundary between the regions with limited undercutting of gate metal beneath the dielectric spacer layer. A subsequent etch removes the gate metal from the transistors in one region while the gate metal in the adjoining region is protected by a buffer layer. Gate dielectric material may also be removed over the boundary between regions.

Processing methods may be performed to form an airgap in a semiconductor structure. The methods may include forming a high-k material on a floor of a trench. The trench may be defined on a semiconductor substrate between sidewalls of a first material and a spacer material. The methods may include forming a gate structure on the high-k material. The gate structure may contact the first material along each sidewall of the trench. The methods may also include etching the first material. The etching may form an airgap adjacent the gate structure.

An integrated circuit device includes a plurality of metal gates each having a metal electrode and a high-κ dielectric and a plurality of polysilicon gates each having a polysilicon electrode and conventional (non high-κ) dielectrics. The polysilicon gates may have adaptations for operation as high voltage gates including thick dielectric layers and area greater than one μm.sup.2. Polysilicon gates with these adaptations may be operative with gate voltages of 10V or higher and may be used in embedded memory devices.

Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a 3D memory device includes a memory stack and a TSC. The memory stack includes a plurality of interleaved conductive layers and dielectric layers. Edges of the interleaved conductive layers and dielectric layers define a staircase structure on a side of the memory stack. The TSC extends vertically through the staircase structure of the memory stack. The TSC includes a conductor layer and a spacer circumscribing the conductor layer.

Various embodiments of the present disclosure are directed towards a semiconductor device. The semiconductor device comprises a source region and a drain region in a substrate and laterally spaced. A gate stack is over the substrate and between the source region and the drain region. The drain region includes two or more first doped regions having a first doping type in the substrate. The drain region further includes one or more second doped regions in the substrate. The first doped regions have a greater concentration of first doping type dopants than the second doped regions, and each of the second doped regions is disposed laterally between two neighboring first doped regions.

A method of manufacturing a memory structure including following steps is provided. Two gate stack structures are formed on a substrate. A conductive material layer is conformally formed on the two gate stack structures. The conductive material layer includes two protrusions located on the two gate stack structures. Hard mask spacers are formed on two sides of each of the two protrusions. A first etching process is performed to remove a portion of the conductive material layer by using the hard mask spacers as a mask. A second etching process is performed to completely remove the hard mask spacers. Then, a third etching process is performed on the conductive material layer to form a first conductive spacer and a second conductive spacer located on one side and the other side of the two gate stack structures and to form a conductive layer located between the two gate stack structures.

A polysilicon-insulator-polysilicon (PIP) structure includes: a first polysilicon region formed on a substrate; a first insulation region formed outside one side of the first polysilicon region and adjoined to the first polysilicon region in a horizontal direction; and a second polysilicon region formed outside one side of the first insulation region. The first polysilicon region, the first insulation region and the second polysilicon region are adjoined in sequence in the horizontal direction. The second polysilicon region is formed outside the first insulation region by a first self-aligned process step, and the first insulation region is formed outside the first polysilicon region by a second self-aligned process step.

Embodiments of the present disclosure disclose a semiconductor device and a method for manufacturing the same. The semiconductor device includes: a substrate; a gate layer located on the substrate; a first conduction layer and a second conduction layer located on the gate layer and including a perovskite as the material thereof; a first source and a first drain spaced apart from each other and connected with either end of the first conduction layer respectively; a second source and a second drain spaced apart from each other and connected with either end of the second conduction layer respectively.

Methods of forming structures including a layer of metal carbon nitride (MCN) and of mitigating metal loss from and/or tuning the layer of metal carbon nitride are disclosed. Systems for forming the layers and mitigating metal loss and structures formed using the methods are also disclosed.

It is an object to provide a ferroelectric thin film having much higher ferroelectric properties than conventional Sc-doped ferroelectric thin film constituted by aluminum nitride and also having stability when applied to practical use, and also to provide an electronic device using the same.

There are provided a ferroelectric thin film represented by a chemical formula M1.sub.1-XM2.sub.XN, wherein M1 is at least one element selected from Al and Ga, M2 is at least one element selected from Mg, Sc, Yb, and Nb, and X is within a range of 0 or more and 1 or less, and also an electronic device using the same.