A DC/DC converter includes: electronic components group including a first capacitor, a high-voltage-side switching element, a low-voltage-side switching element, an inductor, and a second capacitor and constituting a half-bridge circuit; and a substrate including a high-voltage region, a low-voltage region, a connection region, and a pair of ground regions. The first capacitor is mounted across one of the ground regions and the high-voltage region. The high-voltage-side switching element is mounted across the high-voltage region and the connection region. The low-voltage-side switching element is mounted across the connection region and one of the ground regions. The inductor is mounted across the connection region and the low-voltage region. The second capacitor is mounted across the low-voltage region and one of the ground regions.

A DC/DC converter includes: electronic components group including a first capacitor, a high-voltage-side switching element, a low-voltage-side switching element, an inductor, and a second capacitor and constituting a half-bridge circuit; and a substrate including a high-voltage region, a low-voltage region, a connection region, and a pair of ground regions. The first capacitor is mounted across one of the ground regions and the high-voltage region. The high-voltage-side switching element is mounted across the high-voltage region and the connection region. The low-voltage-side switching element is mounted across the connection region and one of the ground regions. The inductor is mounted across the connection region and the low-voltage region. The second capacitor is mounted across the low-voltage region and one of the ground regions.

A semiconductor structure bonding apparatus is disclosed. The apparatus may include a leveling adjustment system configured to provide leveling adjustment of upper and lower block assemblies of the apparatus. In some cases, the leveling adjustment system may include a plurality of threaded posts, differentially threaded adjustment collars, and leveling sleeves. In some instances, the leveling adjustment system further may include a plurality of preload springs configured to provide a given preload capacity and range of adjustment. In some instances, the leveling adjustment system further may include a load cell through which one of the threaded posts may be inserted. In some embodiments, the upper block assembly further may include a reaction plate configured to reduce deformation of the upper block assembly. In some embodiments, the upper block assembly further may include a thermal isolation plate configured to provide compliance deflection and being of monolithic or polylithic construction, as desired.

Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in source/drain regions on fin portions. The fin portions can be located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions can be oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.

The present invention provides a method of manufacturing a bonded wafer, including performing RTA under an atmosphere containing hydrogen on a bonded wafer after separating the bond wafer constituting the bonded wafer, and subsequently performing a sacrificial oxidation process to reduce the thickness of the thin film, wherein the RTA is performed under conditions of a retention start temperature of more than 1150° C. and a retention end temperature of 1150° C. or less. The invention can inhibit the BMD density from increasing and sufficiently flatten the surface of a thin film when the thin film of the bonded wafer is flattened and thinned by the combination of the RTA and sacrificial oxidation processes.

A memory opening can be formed through a multiple tier structure. Each tier structure includes an alternating stack of sacrificial material layers and insulating layers. After formation of a dielectric oxide layer, the memory opening is filled with a sacrificial memory opening fill structure. The sacrificial material layers are removed selective to the insulating layers and the dielectric oxide layer to form backside recesses. Physically exposed portions of the dielectric oxide layer are removed. A backside blocking dielectric and electrically conductive layers are formed in the backside recesses. Subsequently, the sacrificial memory opening fill structure is replaced with a memory stack structure including a plurality of charge storage regions and a semiconductor channel. Hydrogen or deuterium from a dielectric core may then be outdiffused into the semiconductor channel.

A substrate processing method includes preparing a stacked substrate including a first substrate divided into multiple chips, a protective film divided for each of the multiple chips to protect the chip, a second substrate supporting the first substrate, and an adhesive film configured to attach the protective film and the second substrate; reducing adhesive strength of the adhesive film with a light beam configured to penetrate the second substrate; and picking-up, from the adhesive film by a pick-up device, the chip and the protective film with the reduced adhesive strength to the adhesive film.

A method for assembling two substrates by molecular adhesion comprises: a first step (a) of putting first and second substrates in close contact in order to form an assembly having an assembly interface; a second step (b) of reinforcing the degree of adhesion of the assembly beyond a threshold adhesion value at which water is no longer able to diffuse along the assembly interface. The method also comprises a step (c) of anhydrous treatment of the first and second substrates in a treatment atmosphere having a dew point below −10° C., and control of the dew point of a working atmosphere to which the first and second substrates are exposed from the anhydrous treatment step (c) until the end of the second step (b) so as to limit or prevent the appearance of bonding defects at the assembly interface.

Wafer processing methods are provided. The methods may include cutting respective edges of a wafer and an adhesive a predetermined angle before grinding a back surface of the wafer.

In one embodiment, die are singulated from a wafer having a back layer by placing the wafer onto a first carrier substrate with the back layer adjacent the carrier substrate, forming singulation lines through the wafer to expose the back layer within the singulation lines, and using a mechanical device to apply localized pressure to the wafer to separate the back layer in the singulation lines. The localized pressure can be applied through the first carrier substrate proximate to the back layer, or can be applied through a second carrier substrate attached to a front side of the wafer opposite to the back layer. A support structure is used to heat and/or cool at least the first carrier-substrate while the localized pressure is applied.