Patent classifications
H01L21/38
Self-forming spacers using oxidation
A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.
Self-forming spacers using oxidation
A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.
Integrated circuit with frontside and backside conductive layers and exposed backside substrate
An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.
Integrated circuit with frontside and backside conductive layers and exposed backside substrate
An integrated circuit includes multiple backside conductive layers disposed over a backside of a substrate. The multiple backside conductive layers each includes conductive segments. The conductive segments in at least one of the backside conductive layers are configured to transmit one or more power signals. The conductive segments of the multiple backside conductive layers cover select areas of the backside of the substrate, thereby leaving other areas of the backside of the substrate exposed.
Band edge emission enhanced organic light emitting diode with a localized emitter
A light emitting photonic crystal having an organic light emitting diode and methods of making the same are disclosed. An organic light emitting diode disposed within a photonic structure having a band-gap, or stop-band, allows the photonic structure to emit light at wavelengths occurring at the edges of the band-gap. Photonic crystal structures that provide this function may include materials having a refractive index that varies.
INFRARED OPTICAL SENSOR AND MANUFACTURING METHOD THEREOF
Provided is an infrared optical sensor including a substrate, a channel layer on the substrate, optical absorption structures dispersed and disposed on the channel layer, and electrodes disposed on the substrate, and disposed on both sides of the channel layer, wherein the channel layer and the optical absorption structures include transition metal dichalcogenides.
INFRARED OPTICAL SENSOR AND MANUFACTURING METHOD THEREOF
Provided is an infrared optical sensor including a substrate, a channel layer on the substrate, optical absorption structures dispersed and disposed on the channel layer, and electrodes disposed on the substrate, and disposed on both sides of the channel layer, wherein the channel layer and the optical absorption structures include transition metal dichalcogenides.
Low temperature polysilicon thin film transistor and fabricating method thereof and array substrate
A LTPS TFT comprises a substrate, and a buffer layer, a low temperature polysilicon layer, a source contact area, a drain contact area, a gate insulating layer, a gate layer, a dielectric layer, a source and a drain disposed on the substrate successively. The source contact area and the drain contact area are doped with metal ions individually. The source and the drain are connecting with the source and drain contact areas separately through the dielectric layer. The metal ions include at least one of Cu.sup.2+, Al.sup.3+, Mg.sup.2+, Zn.sup.2+ and Ni.sup.2+. A method of fabricating the LTPS TFT is also provided. An annealing is performed for driving individually metal ions of the insulation metal oxide layer into the source contact area and the drain contact area. Thus, the step of implanting p-type ions can be omitted, the procedure can be significantly simplified, and the manufacturing cost can be reduced.
Low temperature polysilicon thin film transistor and fabricating method thereof and array substrate
A LTPS TFT comprises a substrate, and a buffer layer, a low temperature polysilicon layer, a source contact area, a drain contact area, a gate insulating layer, a gate layer, a dielectric layer, a source and a drain disposed on the substrate successively. The source contact area and the drain contact area are doped with metal ions individually. The source and the drain are connecting with the source and drain contact areas separately through the dielectric layer. The metal ions include at least one of Cu.sup.2+, Al.sup.3+, Mg.sup.2+, Zn.sup.2+ and Ni.sup.2+. A method of fabricating the LTPS TFT is also provided. An annealing is performed for driving individually metal ions of the insulation metal oxide layer into the source contact area and the drain contact area. Thus, the step of implanting p-type ions can be omitted, the procedure can be significantly simplified, and the manufacturing cost can be reduced.
METHODS AND APPARATUS FOR GETTERING IMPURITIES IN SEMICONDUCTORS
Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.