Patent classifications
H01L21/44
Method for preparing ohmic contact electrode of gallium nitride-based device
A method for preparing an ohmic contact electrode of a GaN-based device. Said method comprises the following steps: growing a first dielectric layer (203) on an upper surface of a device (S1); implanting silicon ions and/or indium ions in a region of the first dielectric layer (203) corresponding to an ohmic contact electrode region, and in the ohmic contact electrode region of the device (S2); growing a second dielectric layer (206) on an upper surface of the first dielectric layer (203) (S3); activating the silicon ions and/or the indium ions by means of a high temperature annealing process, so as to form an N-type heavy doping (S4); respectively removing portions, corresponding to the ohmic contact electrode region, of the first dielectric layer (203) and the second dielectric layer (206) (S5); growing a metal layer (208) on the upper surface of the ohmic contact electrode region of the device, so as to form an ohmic contact electrode (S6). The ohmic contact electrode prepared by the method can ensure that the metal layer (208) has flat surfaces, smooth and regular edges, and said electrode has stable device breakdown voltage, and is reliable and has a long service life.
Thick-film pastes containing lead-tellurium-lithium-oxides, and their use in the manufacture of semiconductor devices
The present invention provides a thick-film paste for printing the front side of a solar cell device having one or more insulating layers. The thick film paste comprises an electrically conductive metal, and a lead-tellurium-lithium-oxide dispersed in an organic medium.
Semiconductor device and method of bonding semiconductor die to substrate in reconstituted wafer form
A semiconductor device has a plurality of semiconductor die disposed over a carrier. An electrical interconnect, such as a stud bump, is formed over the semiconductor die. The stud bumps are trimmed to a uniform height. A substrate includes a bump over the substrate. The electrical interconnect of the semiconductor die is bonded to the bumps of the substrate while the semiconductor die is disposed over the carrier. An underfill material is deposited between the semiconductor die and substrate. Alternatively, an encapsulant is deposited over the semiconductor die and substrate using a chase mold. The bonding of stud bumps of the semiconductor die to bumps of the substrate is performed using gang reflow or thermocompression while the semiconductor die are in reconstituted wafer form and attached to the carrier to provide a high throughput of the flipchip type interconnect to the substrate.
Method of manufacturing semiconductor device
According to an embodiment, a method of manufacturing a semiconductor device includes forming a first opening that extends from a second surface of a semiconductor substrate opposite to a first surface toward the first surface and extending to a first insulating layer in the semiconductor substrate, performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening, forming a second insulating layer on a side wall of the semiconductor substrate in the first opening, performing a second annealing process after formation of the second insulating layer, forming a second opening that extends to the conductive layer in the first insulating layer through the first opening, and forming a via that is connected to the conductive layer in the first and second openings.
Electronic element and manufacturing method
An electronic element for an electronic apparatus includes a substrate; a bump, disposed on the substrate for electrically connecting the electronic apparatus; and at least one under bump metal layer, disposed between the bump and the substrate for the bump to be attached to the substrate; wherein the UBM layer forms a breach structure.
Semiconductor device and manufacturing method thereof
A flip-chip mounting technique with high reliability is provided in flip-chip mounting using a Cu pillar. In a semiconductor device to be coupled to a mounting board via a Cu pillar, the Cu pillar is caused to have a laminated structure including a pillar layer, a barrier layer, and a bump in this order from below, and the bump is formed to be smaller than the barrier layer.
Methods and apparatus for correcting substrate deformity
Embodiments of methods and apparatus for correcting substrate deformity are provided herein. In some embodiments, a substrate flattening system includes: a first process chamber having a first substrate support and a first showerhead, wherein the first substrate support does not include a chucking mechanism; a first heater disposed in the first substrate support to heat a substrate placed on a first support surface of the first substrate support; a second heater configured to heat a process gas flowing through the first showerhead into a first processing volume of the first process chamber; and a second process chamber having a second substrate support, wherein the second substrate support is not heated, and wherein the first process chamber and the cooling chamber are both non-vacuum chambers.
Apparatus and method of forming self-aligned cuts in mandrel and a non-mandrel lines of an array of metal lines
A method includes providing a structure having a first, second and third hardmask layer and a mandrel layer disposed respectively over a dielectric stack. An array of mandrels, a beta trench and a gamma trench are patterned into the structure. First inner spacers are formed on sidewalls of the beta trench and second inner spacers are formed on sidewalls of the gamma trench. The first and second inner spacers form a portion of a pattern. The pattern is etched into the dielectric stack to form an array of mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in an X direction. The portion of the pattern formed by the first and second inner spacers forms a first pair of cuts in a mandrel line and a second pair of cuts in a non-mandrel line respectively. The cuts are self-aligned in the Y direction.
Apparatus and method of forming self-aligned cuts in a non-mandrel line of an array of metal lines
A method includes providing a structure having a first hardmask layer, second hardmask layer and mandrel layer disposed respectively over a dielectric stack. An array of mandrels is patterned into the mandrel layer. A gamma trench is patterned into the second hardmask layer and between the mandrels. Self-aligned inner spacers are formed on sidewalls of the gamma trench, the inner spacers forming a portion of a pattern. The pattern is etched into the dielectric stack to form an array of alternating mandrel and non-mandrel metal lines extending in a Y direction and being self-aligned in a perpendicular X direction. The portion of the pattern formed by the inner spacers is utilized to form a pair of non-mandrel line cuts in a non-mandrel line. The non-mandrel line cuts are self-aligned in the Y direction.
WAFER PROCESSING APPARATUS
Disclosed herein is a laser processing apparatus including a condenser having a function of spherical aberration. Since the condenser has a function of spherical aberration, the focal point of a laser beam to be focused by the condenser and applied to a wafer can be continuously changed in position along the thickness of the wafer. Accordingly, a uniform shield tunnel composed of a fine hole and an amorphous region surrounding the fine hole can be formed so as to extend from, the front side of the wafer to the back side thereof, by one shot of the laser beam.