Disclosed herein is a laser processing apparatus including a condenser having a function of spherical aberration. Since the condenser has a function of spherical aberration, the focal point of a laser beam to be focused by the condenser and applied to a wafer can be continuously changed in position along the thickness of the wafer. Accordingly, a uniform shield tunnel composed of a fine hole and an amorphous region surrounding the fine hole can be formed so as to extend from, the front side of the wafer to the back side thereof, by one shot of the laser beam.

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a method for forming a microelectronic device includes attaching a microelectronic die to a support member by forming an attachment feature on at least one of a back side of the microelectronic die and the support member. The attachment feature includes a volume of solder material. The method also includes contacting the attachment feature with the other of the microelectronic die and the support member, and reflowing the solder material to join the back side of the die and the support member via the attachment feature. In several embodiments, the attachment feature is not electrically connected to internal active structures of the die.

Disclosed herein are electroplating systems for forming a layer of metal on a wafer which include an electroplating module and a wafer edge imaging system. The electroplating module may include a cell for containing an anode and an electroplating solution during electroplating, and a wafer holder for holding the wafer in the electroplating solution and rotating the wafer during electroplating. The wafer edge imaging system may include a wafer holder for holding and rotating the wafer through different azimuthal orientations, a camera oriented for obtaining multiple azimuthally separated images of a process edge of the wafer while it is held and rotated (the process edge corresponding to the outer edge of the layer of metal formed on the wafer), and image analysis logic for determining an edge exclusion distance, wherein the edge exclusion distance is a distance between the wafer's edge and the process edge.

A power semiconductor substrate comprising an insulating planar base, at least one conductor track and at least one contact area as part of the conductor track, wherein a layer of a metallic material is disposed on the contact area by means of pressure sintering. The associated method comprises the steps of: producing a power semiconductor substrate that includes a planar insulating base, conductor tracks and contact areas; arranging a pasty layer, composed of a metallic material and a solvent, on at least one contact area of the power semiconductor substrate; and applying pressure to the pasty layer.

Semiconductor device manufacturing methods are disclosed. In some embodiments, a method of manufacturing a semiconductor device includes forming a first pattern in a hard mask using a first lithography process, and forming a second pattern in the hard mask using a second lithography process. A protective layer is formed over the hard mask. Portions of the hard mask and portions of the protective layer are altered using a self-aligned double patterning (SADP) method.

An initial etch forms a trench over first contact areas of a plurality of NAND strings, the initial etch also forming individual openings over second contact areas of the plurality of NAND strings. Material is added in the trench to reduce an area of exposed bottom surface of the trench while maintaining the individual openings without substantial reduction of bottom surface area. Subsequent further etching extends the trench and the plurality of individual openings.

A method for forming a low parasitic capacitance contact to a source-drain structure of a fin field effect transistor device. In some embodiments the method includes etching a long trench down to the source-drain structure, the trench being sufficiently long to extend across all the of source-drain regions of the device. A conductive layer is formed on the source-drain structure, and the trench is filled with a first fill material. A second, narrower trench is opened along a portion of the length of the first trench, and filled with a second fill material. The first fill material may be conductive, and may form the contact. If the first fill material is not conductive, a third trench may be opened, in the portion of the first trench not filled with the second fill material, and filled with a conductive material, to form the contact.

A method of manufacturing a semiconductor device includes (a) providing a substrate and (b) forming a film including a first element, a second element and a third element in a same group as the second element on the substrate by performing a cycle a predetermined number of times, the cycle including: (b-1) supplying a halogen-based source gas including the first element to the substrate; (b-2) supplying a first reactive gas including the second element and reactive with the halogen-based source gas; and (b-3) supplying a second reactive gas including the third element without mixing the second reactive gas with the first reactive gas, wherein the second reactive gas is reactive with the halogen-based source gas and unreactive with the first reactive gas.

The present invention provides a TFT substrate manufacturing method and a TFT substrate manufactured with the method. The TFT substrate manufacturing method of the present invention uses a photoresist pattern to serve as a shielding mask to allow a metal layer to be directly oxidized, through the anodic oxidation technology, into a gate insulation layer or a passivation layer, and at the same time, forming electrode patterns of gate or source/drain. The entire operation can be conducted in room temperature and is applicable to a flexible substrate that is not resistant to high temperatures without the involvement of expensive high temperature facility, such as chemical vapor deposition, so as to greatly reduce the operation cost of manufacturing a flexible display device. The TFT substrate manufactured with the present invention shows excellent electrical characteristics and is suitable for a flexible display device.

The present invention provides a TFT substrate manufacturing method and a TFT substrate manufactured with the method. The TFT substrate manufacturing method of the present invention uses a photoresist pattern to serve as a shielding mask to allow a metal layer to be directly oxidized, through the anodic oxidation technology, into a gate insulation layer or a passivation layer, and at the same time, forming electrode patterns of gate or source/drain. The entire operation can be conducted in room temperature and is applicable to a flexible substrate that is not resistant to high temperatures without the involvement of expensive high temperature facility, such as chemical vapor deposition, so as to greatly reduce the operation cost of manufacturing a flexible display device. The TFT substrate manufactured with the present invention shows excellent electrical characteristics and is suitable for a flexible display device.