A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.

A manufacturing method of a display substrate, a display substrate, and a display device. The manufacturing method includes: forming an active layer; forming a gate insulation film layer, a gate film layer and a photoresist film layer; exposing the photoresist film layer to a light and developing the exposed photoresist film layer until the developed photoresist film layer has a thickness of 1.8-2.2 μm and a slope angle not less than 70°; over-etching the gate film layer to form a gate electrode, an orthographic projection of the gate electrode being located within a region of an orthographic projection of the developed photoresist film layer; over-etching the gate insulation film layer by a gaseous corrosion method to form a gate insulation layer; peeling off the photoresist film layer remaining on a surface of the gate electrode; and performing a conductive treatment to the active layer.

Embodiments of the present disclosure are directed to a leadframe package with recesses formed in outer surface of the leads. The recesses are filled with a filler material, such as solder. The filler material in the recesses provides a wetable surface for filler material, such as solder, to adhere to during mounting of the package to another device, such as a printed circuit board (PCB). This enables strong solder joints between the leads of the package and the PCB. It also enables improved visual inspection of the solder joints after the package has been mounted.

A method of forming a self-aligned pattern of vias in a semiconductor device comprises forming a first layer of mandrels, then forming a second layer of mandrels orthogonal to the first layer of mandrels. The layout of the first and second layers of mandrels defines a pattern that can be used to create vias in a semiconductor material. Other embodiments are also described.

An integrated circuit device includes a lower electrode including a niobium (Nb)-containing layer doped with titanium (Ti), a dielectric layer on the lower electrode, and an upper electrode that covers the dielectric layer.

The present application provides a semiconductor package and a manufacturing method thereof. The semiconductor package includes a first device, first electrical connectors, a second device and second electrical connectors. The first device is attached to a package substrate. An active side of the first device die faces toward the package substrate. The first electrical connectors connect the active side of the first device die to the package substrate. The second device die is stacked over the first device die. An active side of the second device die faces toward the package substrate. A portion of the active side of the second device die is outside an area that overlaps the first device die. The second electrical connectors connect the portion of the active side of the second device die to the package substrate.

An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit structure is provided. The memory devices are electrically connected to the integrated circuit. The integrated circuit and the memory devices are stacked, and the memory devices are embedded in the insulating encapsulation. The redistribution circuit structure is disposed on the insulating encapsulation, and the redistribution circuit structure is electrically connected to the integrated circuit and the memory devices. Furthermore, methods for fabricating the integrated fan-out package are also provided.

Fabrication of a physically unclonable function containing semiconductor device by fabricating a first electrode of the semiconductor device, randomly nucleating material regions upon a surface of the first electrode and forming a second electrode upon the first electrode and at least a portion of the randomly nucleated regions.

A film structure, a chip carrier assembly, and a chip carrier device are provided. The film structure includes a film and a plurality of micro-heaters. In which, the film is applied on a substrate, and the plurality of micro-heaters is disposed on top of the film or in the film. The chip carrier assembly includes a circuit substrate and the film structure. In which, the circuit substrate carries a plurality of chips. The chip carrier device includes the chip carrier assembly and a suction unit. In which, the suction unit is arranged above the chip carrier assembly to attach on and transfer the plurality of chips to the circuit substrate. The chips are disposed on the circuit substrate through solder balls, and the micro-heaters heat the solder balls that are in contact with the chips.

Techniques for simultaneously plating features of varying sizes on a semiconductor substrate are provided. In one aspect, a method for electroplating includes: placing a shield over a wafer, offset from a surface of the wafer, which covers portions of the wafer and leaves other portions of the wafer uncovered; and depositing at least one metal onto the wafer by electroplating to simultaneously form metallurgical features of varying sizes on the wafer based on the shield altering local deposition rates for the portions of the wafer covered by the shield. An electroplating apparatus is also provided.