A device including a first metal feature is disposed in a first insulating layer. A second metal feature is disposed in a second insulating layer and separated from the first metal feature by a portion of a first etch stop liner disposed between the first and the second insulating layers. The second metal feature is capacitively coupled to the first metal feature through the first etch stop liner.

A method of manufacturing a semiconductor device includes providing a semiconductor substrate, sequentially forming an etch stop layer and an interlayer dielectric layer on the semiconductor substrate, forming a copper metal interconnect structure in the interlayer dielectric layer, forming a copper layer in the copper metal interconnect structure, forming a cobalt layer on the copper layer, and forming an aluminum nitride layer on the cobalt layer. The stack of cobalt layer and copper layer effectively suppresses electromigration caused by diffusion of the copper layer into the interlayer dielectric layer, improves the adhesion between the copper layer and the etch stop layer, and prevents delamination.

A thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The thin film transistor includes: an active layer, a source-drain metal layer and a diffusion blocking layer located between the active layer and the source-drain metal layer, wherein, the source-drain metal layer includes a source electrode and a drain electrode; the diffusion blocking layer includes a source blocking part corresponding to a position of the source electrode and a drain blocking part corresponding to a position of the drain electrode; and the diffusion blocking layer is doped with different concentrations of nitrogen from a side close to the source-drain metal layer to a side close to the active layer.

A thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The thin film transistor includes: an active layer, a source-drain metal layer and a diffusion blocking layer located between the active layer and the source-drain metal layer, wherein, the source-drain metal layer includes a source electrode and a drain electrode; the diffusion blocking layer includes a source blocking part corresponding to a position of the source electrode and a drain blocking part corresponding to a position of the drain electrode; and the diffusion blocking layer is doped with different concentrations of nitrogen from a side close to the source-drain metal layer to a side close to the active layer.

A composite circuit board includes a composite circuit board unit, a first solder mask formed on a first metal protection layer of the composite circuit board unit, and a second solder mask formed on a second metal protection layer of the composite circuit board unit. Two ends of a first outer conductive circuit are bent back toward each other and spaced apart a predetermined distance to form a first window. Two ends of a second outer conductive circuit are bent back toward each other and spaced apart a predetermined distance to form a second window.

A method of manufacturing a chip module comprises a step of disposing a first electronic element 13 on a first jig 500, a step of disposing a first connector 60 on the first electronic element 13 via a conductive adhesive 5, a step of disposing a second electronic element 23 on the first connector 60 via a conductive adhesive 5, a step of disposing a second connector 70 on a second jig 550, a step of reversing the second jig in a state where the second connector 70 is fixed to the second jig 550 and disposing the second connector 70 on the second electronic element 23 via a conductive adhesive 5, and a step of curing the conductive adhesives 5.

An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

Provided is a semiconductor device which has a double-gate structure with a channel layer made of an oxide semiconductor and is capable of inhibiting the occurrence of hysteresis.

A TFT having a double-gate structure with a channel layer 40 made of an oxide semiconductor uses a passivation film (70), which is a film stack obtained by stacking, sequentially from the side closest to the channel layer (40), a silicon oxide film (71), a first silicon nitride film (73), and a second silicon nitride film (74). In this case, the second silicon nitride film (74) farthest from the channel layer (40) is formed so as to have a higher hydrogen content than the first silicon nitride film (73) closer to the channel layer (40). Thus, it is rendered possible to inhibit the shifting of a threshold voltage of the TFT (100) resulting from hydrogen spreading in the channel layer (40), and at the same time, it is also rendered possible to diminish hysteresis and thereby inhibit the shifting of the threshold voltage caused by hysteresis.

Provided is a semiconductor device which has a double-gate structure with a channel layer made of an oxide semiconductor and is capable of inhibiting the occurrence of hysteresis.

A TFT having a double-gate structure with a channel layer 40 made of an oxide semiconductor uses a passivation film (70), which is a film stack obtained by stacking, sequentially from the side closest to the channel layer (40), a silicon oxide film (71), a first silicon nitride film (73), and a second silicon nitride film (74). In this case, the second silicon nitride film (74) farthest from the channel layer (40) is formed so as to have a higher hydrogen content than the first silicon nitride film (73) closer to the channel layer (40). Thus, it is rendered possible to inhibit the shifting of a threshold voltage of the TFT (100) resulting from hydrogen spreading in the channel layer (40), and at the same time, it is also rendered possible to diminish hysteresis and thereby inhibit the shifting of the threshold voltage caused by hysteresis.

The present invention provides a power module substrate including an insulating substrate, a circuit layer which is formed on one surface of the insulating substrate, and a metal layer which is formed on the other surface of the insulating substrate, in which the circuit layer has a first aluminum layer made of aluminum or an aluminum alloy which is bonded to the insulating substrate and a first copper layer made of copper or a copper alloy which is bonded to the first aluminum layer by solid-phase diffusion, the metal layer has a second aluminum layer made of aluminum or an aluminum alloy, and a relationship between a thickness t.sub.1 of the circuit layer and a thickness t.sub.2 of the second aluminum layer of the metal layer satisfy t.sub.1<t.sub.2.