A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.

There is provided a method for manufacturing a flexible electrode, the method comprising: cleaning a plastic substrate; forming a metal-oxide seed layer on the plastic substrate by sputtering a metal oxide on the plastic substrate; and forming a metal plating layer on the metal oxide seed layer using an electroless plating.

There is provided a method for manufacturing a flexible electrode, the method comprising: cleaning a plastic substrate; forming a metal-oxide seed layer on the plastic substrate by sputtering a metal oxide on the plastic substrate; and forming a metal plating layer on the metal oxide seed layer using an electroless plating.

Methods for depositing a contact metal layer in contact structures of a semiconductor device are provided. In one embodiment, a method for depositing a contact metal layer for forming a contact structure in a semiconductor device is provided. The method comprises performing a cyclic metal deposition process to deposit a contact metal layer on a substrate and annealing the contact metal layer disposed on the substrate. The cyclic metal deposition process comprises exposing the substrate to a deposition precursor gas mixture to deposit a portion of the contact metal layer on the substrate, exposing the portion of the contact metal layer to a plasma treatment process, and repeating the exposing the substrate to a deposition precursor gas mixture and exposing the portion of the contact metal layer to a plasma treatment process until a predetermined thickness of the contact metal layer is achieved.

A reflow enhancement layer is formed in an opening prior to forming and reflowing a contact metal or metal alloy. The reflow enhancement layer facilitates the movement (i.e., flow) of the contact metal or metal alloy during a reflow anneal process such that a void-free metallization structure of the contact metal or metal alloy is provided.

The present disclosure provides a method of manufacturing a semiconductor wafer having a semiconductor-on-insulator (SOI) configuration, the method including providing a semiconductor starting wafer, the semiconductor starting wafer having a base substrate, a semiconductor layer formed over the base substrate and a buried insulating material layer formed between the semiconductor substrate and the base substrate, exposing the semiconductor starting wafer to a first oxidization process, wherein an oxide surface region is formed by oxidizing an upper surface region of the semiconductor layer, thinning the oxide surface region, exposing the semiconductor starting wafer to a second oxidization process, wherein a thickness of the oxide surface region is locally increased, and removing the oxide surface region, wherein the semiconductor layer is exposed.

Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: plating at least one through-assembly via (TAV) over a peripheral region of a conductive seed layer; forming a dam member over a central region of the conductive seed layer; and placing a die over the central region of the conductive seed layer. The dam member may be laterally separated from the die and disposed between the die and the at least one TAV. The method may further include encapsulating the die, the dam member, and the at least one TAV in a polymer material.

A method of manufacturing a semiconductor device may include: forming an opening in a dielectric layer, the opening exposing a non-conductive layer disposed over a semiconductor substrate; forming a self-assembled monolayer (SAM) within the opening and over the non-conductive layer; forming a catalytic layer within the opening and over the SAM; filling the opening having the SAM and the catalytic layer with a conductive material to form a plug; and forming a barrier layer on sidewalls of the plug.

A semiconductor structure that includes: a semiconductor substrate having a semiconductor base and back end of the line (BEOL) wiring layers; a dielectric cap layer on the semiconductor base; trenches on the dielectric cap layer, each of the trenches including dielectric walls, a dielectric bottom in contact with the dielectric cap layer and a metal filling a space between the dielectric walls; air gap openings on the dielectric cap layer and interspersed with the trenches, each air gap opening between the dielectric wall from one metal trench and adjacent to the dielectric wall of a second metal, the dielectric cap layer forming a bottom of the air gap openings; and a second dielectric cap layer formed over the trenches and over the air gap openings, the second dielectric cap layer pinching off each air gap opening.

The present disclosure provides a semiconductor structure. The structure includes a first substrate; a first dielectric layer having a first surface in proximity to the first substrate and a second surface away from the first substrate; a first interconnect penetrating the first surface of the first dielectric layer; and a protection layer extending along a portion of a sidewall of the first interconnect. A thickness of the protection layer is in a range of from about 0.02 μm to about 0.2 μm.