The disclosure provides a method for manufacturing a flexible display panel and a flexible display panel. Wherein the method comprises: binding a flexible substrate with a supporting column matrix on a supporting plate, and fixing the flexible substrate with the supporting plate by a sealant in vacuum, wherein the sealant is disposed at the edge of the supporting column matrix, such that the supporting column matrix is surrounded in a sealed space formed by the sealant, the supporting plate and the flexible substrate; forming a flexible display panel on the flexible substrate; and cutting the supporting plate and the flexible display panel along the inner side of the sealant, such that the flexible display panel separating with the supporting plate. Thus, the flexible substrate can be separated from the supporting plate without damaging devices disposed on the flexible substrate.

Aspects of the disclosure include method of making semiconductor structures. Aspects include providing a semiconductor structure including a plurality of spacer, an organic planarization layer, and a SiARC layer. Aspects also include forming an inverted mask on the semiconductor structure, the inverted mask including an inverted mask opening above a portion of the plurality of spacers and a portion of the TiN layer. Aspects also include eroding the portion of the plurality of spacers below the inverted mask opening. Aspects also include depositing a fill material masking the portion of the plurality of spacers below the inverted mask opening and the portion of the TiN layer below the inverted mask opening to generate a masked TiN layer segment and an unmasked TiN layer segment and removing a portion of the unmasked TiN layer segment.

A process for the manufacture of a composite structure includes the following stages: a) providing a donor substrate comprising a first surface and a support substrate; b) forming a zone of weakening in the donor substrate, the zone of weakening delimiting, with the first surface of the donor substrate, a working layer; c) assembling the support substrate and the donor substrate; d) fracturing the donor substrate along the zone of weakening; and e) thinning the working layer so as to form a thinned working layer. Stage b) is carried out so that the working layer exhibits a thickness profile appropriate for compensating for the nonuniformity in consumption of the working layer during stage e).

A back-side device structure with a silicon-on-insulator substrate that includes a device layer, a buried insulator layer, a trench that extends through the device layer and that partially extends through the buried insulator layer, at least one dielectric layer that is formed on the device layer and includes a first opening that communicates with the trench and a contact plug that fills the trench. A final substrate is connected to the buried insulator layer such that the contact plug contacts metallization of the final substrate. The contact plug is externally connected with a source to provide signals to the back-side device structure through a wire formed in the at least one dielectric layer.

A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

Techniques for fabricating a semiconductor chip having a curved surface may include placing a substantially flat semiconductor chip in a recess surface of a concave mold such that corners or edges of the semiconductor chip are unconstrained or are the only portions of the semiconductor chip in physical contact with the concave mold; and bending the substantially flat semiconductor chip to form a concave shaped semiconductor chip by applying a force on the semiconductor chip toward the bottom of the recessed surface. The corners or edges of the semiconductor chip move or slide relative to the recess surface during the bending.

A method for manufacturing a film support beam includes: providing a substrate having opposed first and second surfaces; coating a sacrificial layer on the first surface of the substrate, and patterning the sacrificial layer; depositing a dielectric film on the sacrificial layer to form a dielectric film layer, and depositing a metal film on the dielectric film layer to form a metal film layer; patterning the metal film layer, and dividing a patterned area of the metal film layer into a metal film pattern of a support beam portion and a metal film pattern of a non-support beam portion, wherein a width of the metal film pattern of the support beam portion is greater than a width of a final support beam pattern, and a width of the metal film pattern of the non-support beam portion is equal to a width of a width of a final non-support beam pattern at the moment; photoetching and etching on the metal film layer and the dielectric film layer to obtain the final support beam pattern, the final non-support beam pattern and a final dielectric film layer, wherein the final dielectric film layer serves as a support film of the final support beam pattern and the final non-support beam pattern; and removing the sacrificial layer.

A method of forming, and corresponding structure, of an LED device where an LED and the contacts for the device are formed on a surface of the substrate, and the substrate is spalled just below the surface of the substrate.

A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without limitation, various aspects of this disclosure provide a process that comprises depositing a thin metal layer on a copper pillar and then mating the copper pillar with another copper element. Atoms of the thin metal layer may, for example, form a substitutional solid solution or intermetallic compounds with copper. A concentration gradient is introduced by the thin metal layer, and diffusion at the CuCu interface begins immediately. The thin metal film and the copper may, for example, diffuse until the interface disappears or substantially disappears.