A charge array wafer includes a plurality of electrical charge storage cells disposed in an array configuration. A programmable amount of charge in each of the electrical charge storage cells causes a predetermined electric field to extend from a charge storage layer, through a passivation layer and into the space above the passivation layer, and the predetermined electric field is operable to attract deposition material to the top surface of the passivation layer. The deposition material may be a gas, a liquid or a powder, having a minimum feature size ranging from tens of nanometers to around five microns. The array of electrical charge storage cells includes an uninterrupted two-dimensional array extending over greater than 100×100 electrical charge storage cells without a select gate and without a bit-line contact positioned between any of the electrical charge storage cells.

An image sensor array formed on a flexible first substrate is supported by a flexible second substrate attached thereto. The second substrate has a top surface with an adhesive thereon for attaching the substrates together. The adhesive is on a portion of the second substrate directly beneath the image sensor array to allow selective formation of the second substrate.

A method for manufacturing a semiconductor on insulator type structure by transfer of a layer from a donor substrate onto a receiver substrate, comprises: a) the supply of the donor substrate and the receiver substrate, b) the formation in the donor substrate of an embrittlement zone delimiting the layer to transfer, c) the bonding of the donor substrate on the receiver substrate, the surface of the donor substrate opposite to the embrittlement zone with respect to the layer to transfer being at the bonding interface, and d) the detachment of the donor substrate along the embrittlement zone. A step of controlled modification of the curvature of the donor substrate and/or the receiver substrate is performed before the bonding step.

A process for handling MEMS wafers includes the steps of: (i) attaching a first carrier substrate to a first side of a MEMS wafer, the first carrier substrate being attached via a first wafer bonding tape and a silicone-free peel tape, the peel tape contacting the first side of the MEMS wafer; (ii) performing wafer processing steps on an opposite second side of the MEMS wafer; (iii) releasing the first carrier substrate from the first side of the MEMS wafer via exposure to an energy source, the energy source selectively releasing the wafer bonding tape from the first side of the MEMS wafer; and (iv) peeling the peel tape away from the first side of the MEMS wafer.

Embodiments relate to the design of an electronic device capable having flexible interconnects that connect together a first body and a second body of the electronic device. The flexible interconnects allow the electrical device to better withstand thermal-mechanical stress during fabrication of the electronic device and user usage of the electronic device.

Described herein is a technique capable of forming a film so as to fill a recess of a substrate. According to one aspect thereof, there is provided a substrate processing apparatus including: a substrate mounting table on which a substrate is placed; an adsorption inhibiting gas supplier configured to supply an adsorption inhibiting gas onto a surface of the substrate from above the substrate mounting table; and a source gas supplier configured to supply a source gas onto the surface of the substrate from above the substrate mounting table, wherein a distance D1 between a gas supply port provided in the adsorption inhibiting gas supplier and the substrate is greater than a distance D2 between a gas supply port provided in the source gas supplier and the substrate.

A wafer processing method includes a sheet bonding step of placing a polyolefin or polyester sheet on a front side of a wafer having a device area where devices are formed so as to be separated by division lines, the sheet having a size capable of covering the device area, and next performing thermocompression bonding to bond the sheet to the front side of the wafer, thereby protecting the front side of the wafer with the sheet. The method further includes a test element group (TEG) cutting step of applying a first laser beam through the sheet to the wafer along each division line thereby cutting a TEG formed on each division line, and a modified layer forming step of applying a second laser beam to a back side of the wafer along each division line, the second laser beam having a transmission wavelength to the wafer, thereby forming a modified layer inside the wafer along each division line.

A component carrier with a stack including at least one electrically insulating layer structure and at least one electrically insulating structure has a tapering blind hole formed in the stack and an electrically conductive plating layer extending along at least part of a horizontal surface of the stack outside of the blind hole and along at least part of a surface of the blind hole. A minimum thickness of the plating layer at a bottom of the blind hole is at least 8 μm.

Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.

Disclosed is a semiconductor device capable of functioning as a memory device. The memory device comprises a plurality of memory cells, and each of the memory cells contains a first transistor and a second transistor. The first transistor is provided over a substrate containing a semiconductor material and has a channel formation region in the substrate. The second transistor has an oxide semiconductor layer. The gate electrode of the first transistor and one of the source and drain electrodes of the second transistor are electrically connected to each other. The extremely low off current of the second transistor allows the data stored in the memory cell to be retained for a significantly long time even in the absence of supply of electric power.