An opto-electronic package is described. The opto-electronic package is manufactured using a fan out wafer level packaging to produce dies/frames which include connection features. Additional structures such as heat exchanged structures are joined to a connection component and affixed to packages, using the connection features, to provide structural support and heat exchange to heat generating components in the package, among other functions.

In some embodiments, the present disclosure relates to an integrated chip (IC), including a substrate, a first die disposed over the substrate, a metal wire attached to a frontside of the first die, and a first plurality of die stopper bumps disposed along a backside of the first die and configured to control an angle of operation of the first die. The first plurality of die stopper bumps directly contacts a backside surface of the first die.

A semiconductor package structure includes a first redistribution layer, a plurality of conductive connectors, a chip, and an encapsulant. The first redistribution layer has a first surface and a second surface opposite to the first surface. The first redistribution layer includes at least one conductive pattern and at least one dielectric layer stacked on each other. The conductive pattern includes a plurality of landing pads, and each of the landing pads is separated from the dielectric layer. The conductive connectors are located on the first surface. Each of the conductive connectors is corresponding to and electrically connected to one of the landing pads. The chip is located on the first surface. The chip is electrically connected to the first redistribution layer. The encapsulant encapsulates the chip and the conductive connectors. A manufacturing method of a semiconductor package structure is also provided.

Several embodiments of the present technology are described with reference to a semiconductor apparatus. In some embodiments of the present technology, a semiconductor apparatus includes a stack of semiconductor dies attached to a thermal transfer structure. The thermal transfer structure conducts heat away from the stack of semiconductor dies. Additionally, the assembly can include molded walls to support the thermal transfer structure.

A driver board assembly includes first and second substrates, one or more power device assemblies and a cooling manifold. At least one jet impingement assembly is formed on a first surface of the first substrate and includes an impingement receiving portion that is at least partially circumferentially surrounded by a plurality of fluid microchannels that extend radially from the impingement receiving portion along the first surface. The second substrate is bonded onto the first substrate. The second substrate surface has a recess. The plurality of receiving contours are etched within the first surface of the first substrate. The one or more power device assemblies are bonded into the recess of the second substrate. A first cooling surface of the cooling manifold is bonded to the first surface such that the first cooling surface bonds within the plurality of receiving contours within the first surface of the first substrate.

A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.

According to the various aspects, a multi-chip semiconductor package includes a package substrate, an interconnect frame extending beyond a first side edge of the package substrate, the interconnect frame including a bottom surface positioned over and coupled to a top surface of the package substrate, a first semiconductor device positioned at least partially over and coupled to the interconnect frame, and a second semiconductor device positioned on the bottom surface of the interconnect frame alongside of the package substrate. The interconnect frame further includes a redistribution layer and a frame construct layer, and a plurality of vias coupled to the redistribution layer, with the frame construct layer further includes a recessed area, and the first semiconductor device is positioned in the recessed area.

A film package includes a base substrate having a bottom surface that includes a first portion and a second portion that are spaced apart from each other. First pad wires are disposed on the first portion of the bottom surface of the base substrate. Second pad wires are disposed on the second portion of the bottom surface of the base substrate. A light blocking member is disposed between the first pad wires and the second pad wires.

A driver board assembly includes first and second substrates, one or more power device assemblies and a cooling manifold. At least one jet impingement assembly is formed on a first surface of the first substrate and includes an impingement receiving portion that is at least partially circumferentially surrounded by a plurality of fluid microchannels that extend radially from the impingement receiving portion along the first surface. The second substrate is bonded onto the first substrate. The second substrate surface has a recess. The plurality of receiving contours are etched within the first surface of the first substrate. The one or more power device assemblies are bonded into the recess of the second substrate. A first cooling surface of the cooling manifold is bonded to the first surface such that the first cooling surface bonds within the plurality of receiving contours within the first surface of the first substrate.

A driver board assembly includes first and second substrates, one or more power device assemblies and a cooling manifold. At least one jet impingement assembly is formed on a first surface of the first substrate and includes an impingement receiving portion that is at least partially circumferentially surrounded by a plurality of fluid microchannels that extend radially from the impingement receiving portion along the first surface. The second substrate is bonded onto the first substrate. The second substrate surface has a recess. The plurality of receiving contours are etched within the first surface of the first substrate. The one or more power device assemblies are bonded into the recess of the second substrate. A first cooling surface of the cooling manifold is bonded to the first surface such that the first cooling surface bonds within the plurality of receiving contours within the first surface of the first substrate.