H01L21/4803

FLIP-CHIP PACKAGE WITH REDUCED UNDERFILL AREA

A flip-chip package and a method for assembling a flip-chip package includes positioning the die on a substrate and introducing an underfill material into a space between the die and the substrate, where a portion of the underfill material extends beyond an edge of the die and forms a fillet that at least partially surrounds the die. The underfill material is cured, and a portion of the fillet is removed to reduce the area of the fillet.

Semiconductor device and corresponding method

A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Direct growth methods for preparing diamond-assisted heat-dissipation silicon carbide substrates of GaN-HEMTs

Direct growth methods for preparing diamond-assisted heat-dissipation silicon carbide substrates of GaN-HEMTs are disclosed. In an embodiment, the direct growth method includes the following steps: (1) etching holes in a surface of a silicon carbide substrate to produce a silicon carbide wafer; (2) ultrasonic cleaning the produced silicon carbide wafer; (3) establishing an auxiliary nucleation point on a surface of the silicon carbide wafer; (4) depositing a diamond layer; (5) removing the portion of the diamond layer on the upper surface while retaining the portion of the diamond layer in the holes; (6) ultrasonic cleaning; and (7) depositing diamond in the holes on the silicon carbide wafer until the holes are fully filled.

Silicon Heat-Dissipation Package For Compact Electronic Devices
20210225726 · 2021-07-22 ·

Embodiments of a silicon heat-dissipation package for compact electronic devices are described. In one aspect, a device includes first and second silicon cover plates. The first silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The second silicon cover plate has a first primary side and a second primary side opposite the first primary side thereof. The first primary side of the second silicon cover plate includes an indentation configured to accommodate an electronic device therein. The first primary side of the second silicon cover plate is configured to mate with the second primary side of the first silicon cover plate when the first silicon cover plate and the second silicon cover plate are joined together with the electronic device sandwiched therebetween.

Method of forming a dummy die of an integrated circuit having an embedded annular structure

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Semiconductor package with inner and outer cavities

A semiconductor package structure includes a substrate, a semiconductor die, a lid and a cap. The semiconductor die is disposed on the substrate. The lid is disposed on the substrate. The cap is disposed on the lid. The substrate, the lid and the cap define a cavity in which the semiconductor die is disposed, and a pressure in the cavity is greater than an atmospheric pressure outside the cavity.

Antenna Module

An antenna module Includes a first substrate, a second substrate, the second substrate including at least one cavity at one of the first main surface. The first substrate includes at feast an RF antenna element and/or an RF chip and/or an RF conductive trace, which are arranged on the first main surface of the substrate. The first substrate is connected, with its first main surface, to the first main surface of the second substrate so that the RF elements project into the at least one cavity.

RADIO-FREQUENCY DEVICE COMPRISING SEMICONDUCTOR DEVICE AND WAVEGUIDE COMPONENT
20210225719 · 2021-07-22 ·

A radio-frequency device comprises a semiconductor device, comprising a radio-frequency chip, and a first connection element, which is configured to mechanically and electrically connect the semiconductor device to a circuit board. The radio-frequency device furthermore comprises a waveguide component arranged over the semiconductor device, comprising a waveguide embodied in the waveguide component, and a second connection element, which mechanically connects the waveguide component to the semiconductor device. At least one from the first connection element or the second connection element is embodied in an elastic fashion.

METHODS OF FORMING INTEGRATED CIRCUIT DEVICES USING CUTTING TOOLS TO EXPOSE METALIZATION PADS THROUGH A CAP STRUCTURE AND RELATED CUTTING DEVICES
20210249272 · 2021-08-12 ·

A method of fabricating a semiconductor device can include providing an integrated circuit electrically coupled to a metallization pad on a semiconductor wafer, the integrated circuit and the metallization pad covered by a cap structure. A channel can be cut in a portion of the cap structure that covers the metallization pad using a cutting tool having a tip surface and a beveled side surface to expose an upper surface of the metallization pad in the channel extending in a first direction and a conductive material can be deposited in the channel to ohmically contact the upper surface of the metallization pad in the channel.