A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

The present invention includes a chip, a plastic film layer, and an electroplated layer. A front side and a back side of the chip each comprises a signal contact. The plastic film layer covers the chip and includes a first via and a second via. The first via is formed adjacent to the chip, and the second via is formed extending to the signal contact of the front side. A conductive layer is added in the first and the second via. The conductive layer in the second via is electrically connected to the signal contact of the front side. Through the electroplated layer, the signal contact on the back side is electrically connected to the conductive layer in the first via. The conductive layer protrudes from the plastic film layer as conductive terminals. The present invention achieves electrical connection of the chip without using expensive die bonding materials.

An integrated circuit (IC) package includes a die having a interface region situated on a surface of the die. The interface region is configured to be exposed to an environment of the IC package. The IC package also includes a metal wall mounted on the surface of the die that circumscribes the interface region and extends from the surface of the die to a wall height. The metal wall has a first region and a second region that is stacked on the first region, the first region having a first thickness and the second region having a second thickness. The second thickness is greater than the first thickness. The IC package further includes a molding encasing a remaining portion of the die. The molding has a height that extends from the surface of the die to a level that is less than the wall height of the metal wall.

A semiconductor device includes an insulating layer, a conductive layer stacking with the insulating layer, a spacer structure through the conductive layer and in contact with the insulating layer, a contact structure in the spacer structure and extending vertically through the insulating layer, and a channel structure including a semiconductor channel, a portion of the semiconductor channel being in contact with the conductive layer. The contact structure includes a first contact portion and a second contact portion in contact with each other.

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

A bus bar includes a laminated body formed by directly laminating a flat plate-shaped first conductive plate, flat plate-shaped insulating sheet, and flat plate-shaped second conductive plate. The laminated body has main terminal connection parts into which end portions of external connection terminals are inserted, and is sealed in a sealing body, except the main terminal connection parts. The first conductive plate, insulating sheet, and second conductive plate are pressurized toward the insulating sheet in the lamination direction of the laminated body so that volumes of air spaces inside the insulating sheet (and air spaces between the first conductive plate and the insulating sheet and between the second conductive plate and the insulating sheet) are compressed.

A semiconductor apparatus includes: (i) a semiconductor device; (ii) a first external connection terminal configured to be connected to the semiconductor device, and includes a first surface; and a second surface; and (iii) an insulating resin enclosure. The first external connection terminal includes: a base part that is embedded in the insulating resin enclosure; and a protruding part that protrudes from the inner wall of the insulating resin enclosure. The second surface includes: a first part that corresponds to the protruding part; and a second part that corresponds to the base part and is exposed by the first recessed part. The first part and the second part are continuous with each other along a second direction. The first and second extending parts are spaced apart from each other in a third direction. Each of the first and second extending parts extends along the first direction from a position corresponding to the second surface of the first external connection terminal.

A three-dimensional (3D) integrated circuit (IC) includes a first die. The first die includes a 3D stacked capacitor on a first surface of the first die and coupled to a power distribution network (PDN) of the first die. The 3D IC also includes a second die stacked on the first surface of the first die, proximate the 3D stacked capacitor on the first surface of the first die. The 3D IC further includes active circuitry coupled to the 3D stacked capacitor through the PDN of the first die.

A semiconductor device has a shielding layer over a semiconductor package. A plurality of slot lines define a location to form a slot in the shielding layer. The slot is formed in the shielding layer by cutting along the slot lines with a laser controlled by a scanner to read the slot lines. The slot lines include a left boundary slot line and right boundary slot line. The slot can be cut in the shielding layer by performing an edge cut along the slot lines, and performing a peel back to form the slot in the shielding layer. Alternatively, the slot can be cut in the shielding layer by performing a first cut in a first direction along the slot lines, and performing a second cut in a second direction opposite the first direction along the slot lines to form the slot in the shielding layer.

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.