A semiconductor device is formed using a jig. The jig includes a metal frame, a polymer film, and an adhesive layer disposed between the metal frame and polymer film. An opening is formed through the adhesive layer and polymer film. A groove is formed around the opening. A semiconductor package is disposed on the jig over the opening with a side surface of the semiconductor package adjacent to the groove. A shielding layer is formed over the semiconductor package and jig. The semiconductor package is removed from the jig.

According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region, where the first region defines at least a portion of at least one first transistor and the second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one conductive pad of the at least one first transistor contacting the first region of the wafer substrate, at least one conductive pad of the at least one second transistor contacting the second region of the wafer substrate, a backplate coupled to the wafer substrate, and an encapsulation material, where the encapsulation material has a portion contacting the backplate, and the encapsulation material includes a portion located within the isolation area.

Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

A packaged semiconductor module comprises a substrate having a ground plane, an electronic device mounted on a surface of the substrate, a bond pad disposed on the surface of the substrate and electrically connected to the ground plane, a mold compound covering the electronic device, a conductive post disposed on a side of the electronic device, the conductive post extending from the bond pad and at least partially through the mold compound, and a conductive layer disposed on the mold compound and electrically coupled to the conductive post and to the ground plane, the conductive post, the conductive layer, and the ground plane together forming the integrated electromagnetic interference shield, the conductive post extending from the bond pad to the conductive layer in a direction perpendicular to a plane defined by the surface of the substrate.

A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

An insulated busbar includes a plate conductor and insulating films which cover the plate conductor. The insulated busbar further includes conductive films which are formed on inside surfaces of the insulating films so as to be in contact with the plate conductor and which cover a vacant space between an end portion of the plate conductor and the insulating films.

A semiconductor structure includes a plurality of vias and a metal layer. The vias disposed on a semiconductor substrate. The metal layer has a plurality of metal lines and at least one transmission gate line region. The metal lines are connected to the vias. The at least one transmission gate line region is connected to at least one transmission gate corresponding to at least one transmission gate circuit. The transmission gate line region includes at least one different-net via pair. The different-net via pair has two metal lines and each of the two metal lines is connected to a via respectively. The two metal lines extend along a first axis but toward opposite directions. A distance between the two vias of the different-net via pair is within about 1.5 poly pitch.

A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.

A chip encapsulation structure, including: a wafer provided with a groove; a first metal wire arranged on surfaces of the groove and the wafer; a metal solder ball arranged on the first metal wire or on a metal pad of the chip, and is configured to solder the metal pad of the chip to the first metal wire; a first plastic encapsulation film covering upper surfaces of the wafer, the chip and the first metal wire, and entering a gap between a periphery of a functional area of the chip and the first metal wire, so as to form a closed cavity among the wafer, the groove and the chip; an inductive structure arranged on an upper surface of the first plastic encapsulation film and/or a lower surface of the wafer, and connected to the chip through the first metal wire; and a pad arranged on the inductive structure.

A method for manufacturing a semiconductor structures is provided. The method includes forming a first hybrid bonding layer over a first wafer having a logic structure, forming a second hybrid bonding layer over a second wafer having a first capacitor structure, bonding the first wafer and the second wafer through a hybrid bonding operation to connect the first hybrid bonding layer and the second hybrid bonding layer, thereby obtaining a first bonded wafer, and the first capacitor structure is electrically connected to the logic structure through the first hybrid bonding layer and the second hybrid bonding layer, and singulating the first bonded wafer to obtain a plurality of semiconductor structures.