An electronic power module, including at least one semiconductor component, which is arranged on a support, as well as a cooling element, which is in thermal contact with the semiconductor component, wherein the support includes a semiconductor material and, at the same time, serves as a cooling element.

An IC package structure and associated packaging method. The IC package structure may include an array of package units formed into a panel, wherein each one of the array of package units comprises at least one IC chip/IC die. Each IC chip/IC die may be at least partially covered and wrapped by an encapsulation layer having one or more openings to expose entire or at least a portion of a back surface of each IC chip/IC die. A metal layer may be electroplated on entire back side of the IC package structure to fill the openings in the encapsulation layer so that the metal layer is in direct contact with the exposed portions of the back surface of each IC chip/IC die.

A semiconductor device has a semiconductor package including a substrate with a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A metal mask having a fiducial marker is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The metal mask is removed after forming the shielding layer.

A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.

A method for fabricating a semiconductor device includes: forming a first bonding layer on a first wafer and an etching mask on the first bonding layer; etching an edge portion of the first bonding layer by using the etching mask, such that a portion of the first wafer is exposed; removing the etching mask; and bonding a second wafer to the first bonding layer.

Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

A semiconductor device has a substrate including a terminal and an insulating layer formed over the terminal. An electrical component is disposed over the substrate. An encapsulant is deposited over the electrical component and substrate. A portion of the insulating layer over the terminal is exposed from the encapsulant. A shielding layer is formed over the encapsulant and terminal. A portion of the shielding layer is removed to expose the portion of the insulating layer. The portion of the insulating layer is removed to expose the terminal. The portion of the shielding layer and the portion of the insulating layer can be removed by laser ablation.

An integrated circuit package that includes a leadframe and a mold compound encapsulating at least a portion of the leadframe. The mold compound includes a cavity open at a bottom surface of the mold compound that exposes a bottom surface of the leadframe. A thermally conductive and electrically insulating isolation layer is locked within the bottom cavity of the mold compound and contacts the bottom surface of the leadframe.

Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.