A semiconductor device package includes a substrate, a first circuit layer and a second circuit layer. The first circuit layer is disposed on the substrate. The first circuit layer has a plurality of dielectric layers and a first through via penetrating the dielectric layers and electrically connected to the substrate. The second circuit layer is disposed on the first circuit layer. The second circuit layer has a plurality of dielectric layers and a second through via penetrating the dielectric layers and electrically connected to the first circuit layer.

Methods for protecting edges of semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, a plurality of trenches may be formed on a front side of a substrate including a plurality of semiconductor dies. Individual trenches may correspond to scribe lines of the substrate where each trench includes a depth greater than a final thickness of the semiconductor dies. A dielectric layer may be formed on sidewalls of the trenches, thereby protecting the edges of the semiconductor dies, prior to filling the trenches with an adhesive material. Subsequently, the substrate may be thinned from a back side such that the adhesive material in the trenches may be exposed from the back side. The adhesive material may be removed to singulate individual semiconductor dies of the plurality from the substrate.

The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a semiconductor structure, a conductive trace and a tenting structure. The semiconductor structure has a first surface, a second surface and a third surface extending between the first surface and the second surface, and the first surface, the second surface and the third surface define a through-silicon via recessed from the first surface. The conductive trace is disposed adjacent to the first surface, the second surface and the third surface of the semiconductor structure. The tenting structure covering the TSV of the semiconductor structure. A cavity is defined by the tenting structure and the TSV.

An electronic structure, an electronic package structure and method of manufacturing an electronic device are provided. The electronic structure includes a carrier and a protection layer. The carrier includes a first pad, a second pad and a first dielectric layer. The first pad is at a side of the carrier and configured to bond with a conductive pad. The second pad is at the side of carrier and configured to electrically connect an exterior circuit. The first dielectric layer includes a first portion around the first pad and a second portion around the second pad, wherein a top surface of the first portion and a top surface of the second portion are substantially coplanar. The protection layer is on the second pad and covers the second pad.

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Embodiments of methods for forming contact structures and semiconductor devices thereof are disclosed. In an example, a semiconductor device includes an insulating layer, a conductive layer over the insulating layer, and a spacer structure in the conductive layer and in contact with the insulating layer. The semiconductor device also includes a first contact structure in the spacer structure and extending vertically through the insulating layer. The first contact structure includes a first contact portion and a second contact portion in contact with each other. An upper surface of the second contact portion is coplanar with an upper surface of the conductive layer.

An apparatus is provided, comprising a substrate with a frontside and a backside opposite the frontside; control circuitry disposed over the frontside of the substrate; a memory array disposed over and electrically coupled to the control circuitry; a through-silicon via (TSV) disposed under the memory array, the TSV extending through the substrate from the control circuitry to the backside of the substrate; and a bond pad disposed on the backside of the substrate and electrically coupled to the control circuitry via the TSV.

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.