Some embodiments include a method of forming an integrated assembly. Semiconductor material is patterned into a configuration which includes a set of first upwardly-projecting structures spaced from one another by first gaps, and a second upwardly-projecting structure spaced from the set by a second gap. The second gap is larger than the first gaps. Conductive material is formed along the first and second upwardly-projecting structures and within the first and second gaps. First and second segments of protective material are formed over regions of the conductive material within the second gap, and then an etch is utilized to pattern the conductive material into first conductive structures within the first gaps and into second conductive structures within the second gap. Some embodiments include integrated assemblies.

An integrated circuit (IC) package comprising a die having a front side and a back side. A solder thermal interface material (STIM) comprising a first metal is over the backside. The TIM has a thermal conductivity of not less than 40 W/mK; and a die backside material (DBM) comprising a second metal over the STIM, wherein the DBM has a CTE of not less than 18×10.sup.−6 m/mK, wherein an interface between the STIM and the DBM comprises at least one intermetallic compound (IMC) of the first metal and the second metal.

Method for interconnecting components of an electronic system comprising the steps of: a) depositing a sintering solution onto a first component in order to form an interconnection layer, the sintering solution comprising a solvent, metal nanoparticles dispersed in the solvent, and a stabilizing agent adsorbed onto the metal nanoparticles, more than 95.0%, preferably more than 99.0% of the mass of the metal nanoparticles comprising a metal selected from silver, gold, copper and alloys thereof and having a polyhedral shape with an aspect ratio of more than 0.8, b) eliminating, at least partially, the solvent from the interconnection layer such as to form at least one ordered agglomerate in which the metal nanoparticles are regularly disposed in three axes, the stabilizing agent binding them together and maintaining at least a portion of the metal nanoparticles at a distance from each other, c) debinding and sintering the interconnection layer, and d) depositing a second component in contact with the interconnection layer before or during debinding or sintering.

Method for interconnecting components of an electronic system, the method comprising the steps of: a) depositing a sintering solution onto a first component in order to form an interconnection layer, the sintering solution comprising a solvent, metal nanoparticles dispersed in the solvent, and a stabilizing agent adsorbed onto the metal nanoparticles. the metal nanoparticles comprising for more than 95.0%, preferably for more than 99.0% of their mass a metal selected from silver, gold, copper and alloys thereof and having a polyhedral shape with an aspect ratio of more than 0.8, b) eliminating, at least partially, the solvent from the interconnection layer such as to form at least one agglomerate in which the stabilizing agent binds them together and maintains at least a portion of the metal nanoparticles at a distance from each other, c) debinding and sintering the interconnection layer by bringing the agglomerate into contact with at least one destabilizing agent configured to desorb the stabilizing agent from the metal nanoparticles in order to aggregate and coalesce said metal nanoparticles between themselves, and d) depositing a second component in contact with the interconnection layer before or during debinding or sintering.

A power electronic switching device has a substrate facing in a normal direction with a first and a second conductive track, and a power semiconductor component is arranged on the first conductive track by an electrically conductive connection. The power semiconductor component has a laterally surrounding edge and an edge region and a contact region on its first primary side facing away from the substrate, and with a three-dimensionally preformed insulation molding that has an overlap segment, a connection segment and an extension segment, wherein the overlap segment, starting from the edge partially overlaps the edge region of the power semiconductor component.

Some features pertain to a package, comprising a substrate, an electronic component coupled to the substrate, a mold at least partially surrounding the electronic component and a first shield over the mold, and a second shield over the first shield, the first shield made of a material selected to have a high permeability shield. The package includes an enhanced electromagnetic shield.

An IC device package includes an IC device that is connected to a lid by a thermal interface material (TIM). A catalyst material is formed upon one or more regions upon an upper surface of the IC device and/or an under surface of the lid. The catalyst material increases the rate of crosslinking of polymer chains of the TIM during TIM curing and/or increases the strength of crosslinks that link polymer chains of the TIM during TIM curing. The catalytically enhanced regions have a higher coefficient of heat transfer relative to non-catalytically enhanced regions. Therefore, the catalytically enhanced regions efficiently transfer heat from the IC device to the lid.

An electronic device is provided. The electronic device includes a first substrate. The electronic device also includes a multilayer electrode disposed on the first substrate. The multilayer electrode includes a first conductive layer, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer. The electronic device further includes a second substrate facing the first substrate. In addition, the electronic device includes a working medium disposed between the first substrate and the second substrate. The chemical electromotive force of the second conductive layer is between that of the first conductive layer and the third conductive layer.

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

A method of forming an inverse opal structure along a substrate that includes depositing polymer spheres along the substrate and electroplating the substrate and spheres at a first current density to form a first solid metal layer such that the spheres are raised from the substrate. The method includes electroplating the substrate and the spheres at a second current density to diffuse metals from the substrate and deposit the metal about the spheres. The second current density is greater than the first current density. The method includes electroplating the substrate and spheres to form a second solid metal layer disposed over the spheres, and removing the spheres to form the inverse opal structure disposed between the first and second solid metal layers. The first and second solid metal layers define planar interface surfaces disposed over a porous structure of the inverse opal structure.