Semiconductor packages having a sealant bridge between an integrated heat spreader and a package substrate are described. In an embodiment, a semiconductor package includes a sealant bridge anchoring the integrated heat spreader to the package substrate at locations within an overhang gap laterally between a semiconductor die and a sidewall of the integrated heat spreader. The sealant bridge extends between a top wall of the integrated heat spreader and a die side component, such as a functional electronic component or a non-functional component, or a satellite chip on the package substrate. The sealant bridge modulates warpage or stress in thermal interface material joints to reduce thermal degradation of the semiconductor package.

A bonding method is capable of realizing high bonding strength and connection reliability even at a connection part in a high temperature area by means of simple operation low temperature bonding. The method includes a first step wherein, on at least one of the bonded surfaces of two materials to be bonded having a smooth surface, a thin film of noble metal with a volume diffusion coefficient greater than that of the base metal of the material to be bonded is formed using an atomic layer deposition method at a vacuum of 1.0 Pa or higher, a second step wherein a laminate is formed by overlapping the two materials to be bonded so that the bonded surfaces of the two materials are connected through the thin film, and a third step wherein the two materials to be bonded are bonded by holding the laminate at a predetermined temperature.

According to various aspects and embodiments, a system and method for packaging an electronic device is disclosed. One example of the method comprises depositing a layer of temporary bonding material onto a surface of a first substrate, depositing a layer of structure material onto a surface of the layer of temporary bonding material, masking at least a portion of the structure material to define an unmasked portion and a masked portion of the structure material, exposing the unmasked portion of the structure material to a source of light, removing the masked portion of the structure material, bonding at least a portion of a surface of a second substrate to the unmasked portion of the structure material, and removing the first substrate from the unmasked portion of the structure material.

A multilayer substrate includes a component mounting substrate having component mounting and non-mounting surfaces and including connection pads on both the mounting surfaces, a sealing resin layer having an upper surface in close contact with the non-mounting surface and a flat lower surface, a semiconductor element having an electrode formation surface on which electrodes are formed, and embedded in the sealing resin layer with the electrode formation surface exposed at the flat lower surface, an insulating layer formed in close contact with the electrode formation surface and the flat lower surface, through-holes continuously penetrating through the insulating layer and the sealing resin layer and having bottom ends defined by the connection pads on the non-mounting substrate, via holes penetrating through the insulating layer and having bottom ends defined by the electrodes, and wiring conductors formed inside the through-holes and the via holes and on a surface of the insulating layer.

A multilayer substrate includes a component mounting substrate having component mounting and non-mounting surfaces and including connection pads on both the mounting surfaces, a sealing resin layer having an upper surface in close contact with the non-mounting surface and a flat lower surface, a semiconductor element having an electrode formation surface on which electrodes are formed, and embedded in the sealing resin layer with the electrode formation surface exposed at the flat lower surface, an insulating layer formed in close contact with the electrode formation surface and the flat lower surface, through-holes continuously penetrating through the insulating layer and the sealing resin layer and having bottom ends defined by the connection pads on the non-mounting substrate, via holes penetrating through the insulating layer and having bottom ends defined by the electrodes, and wiring conductors formed inside the through-holes and the via holes and on a surface of the insulating layer.

A semiconductor integrated circuit device includes a fuse element that can be laser trimmed to adjust the characteristics of the semiconductor integrated circuit device, The semiconductor integrated circuit device includes an interlayer insulating film above the fuse element, and the thickness of the interlayer insulating film is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The laser trimming processing is thus stabilized without needing a high level of dry etching stabilization control.

A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

The present invention provides a conductive bonded assembly utilizing particles of Ni or an Ni alloy as conductive particles so as to enable firing under non-pressing conditions and further realize an excellent bonding strength, electron migration characteristic, and ion migration characteristic. The conductive bonded assembly of the present invention is a conductive bonded assembly of an electronic component which has a first bondable member (for example, electrode material), a second bondable member (for example, a semiconductor device on an Si or SiC substrate), and a conductive bonding layer bonding these bondable members together, where the bonding layer is an Ni sintered body formed by a sintered body of Ni particles which has a porosity of 30% or less, and, further, can be obtained by heating and sintering the Ni particles at the time of firing where the Ni sintered bonding layer is formed.

A printed wiring board includes a support plate, and a build-up wiring layer including resin insulating layers and conductor layers and having a first surface and a second surface on the opposite side with respect to the first surface such that the support plate is positioned on the first surface of the build-up wiring layer. The resin insulating layers in the build-up wiring layer include a first resin insulating layer that forms the second surface of the build-up wiring layer, and the build-up wiring layer includes first conductor pads embedded in the first resin insulating layer such that each of the first conductor pads has an exposed surface exposed from the second surface of the build-up wiring layer.

A printed wiring board includes a support plate, and a build-up wiring layer including resin insulating layers and conductor layers and having a first surface and a second surface on the opposite side with respect to the first surface such that the support plate is positioned on the first surface of the build-up wiring layer. The resin insulating layers in the build-up wiring layer include a first resin insulating layer that forms the second surface of the build-up wiring layer, and the build-up wiring layer includes first conductor pads embedded in the first resin insulating layer such that each of the first conductor pads has an exposed surface exposed from the second surface of the build-up wiring layer.