A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

A method for packaging an integrated circuit chip includes the steps of: a) providing a plurality of dies and a lead frame which includes a plurality of bonding parts each having a die pad, a plurality of leads each having an end region disposed on and connected to the die pad, and a plurality of bumps each disposed on the end region of a respective one of the leads; b) transferring each of the dies to the die pad of a respective one of the bonding parts to permit each of the dies to be flipped on the respective bonding part; and c) hot pressing each of the dies and the die pad of a respective one of the bonding parts to permit each of the dies to be bonded to the bumps of the respective bonding part.

A semiconductor device includes a substrate that includes an opening extending through a thickness of the substrate, a frame that includes an integrated circuit (IC) die pad in the opening and a plurality of arms extending outwardly from the IC die pad, an IC mounted on the IC die pad, a plurality of bonding elements electrically coupling the substrate with the IC without the frame being an intermediary coupling element, and an encapsulant surrounding the IC, the plurality of bonding elements, and the plurality of arms. The substrate has a first major surface and a second major surface. Each arm is devoid of a contact pad. Each arm has a distal end coupled to the first major surface of the substrate, and each arm has a proximal end disposed over the first major surface of the substrate.

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a first die at least partially embedded in a first encapsulation layer and a second die at least partially embedded in a second encapsulation layer. The first die may have a first plurality of die-level interconnect structures disposed at a first side of the first encapsulation layer. The IC package may also include a plurality of electrical routing features at least partially embedded in the first encapsulation layer and configured to route electrical signals between a first and second side of the first encapsulation layer. The second side may be disposed opposite to the first side. The second die may have a second plurality of die-level interconnect structures that may be electrically coupled with at least a subset of the plurality of electrical routing features by bonding wires.

A semiconductor package device includes a substrate, an electronic component, and a thermal conductive layer. The electronic component is disposed on the substrate and includes a first surface facing away from the substrate. The thermal conductive layer is disposed above the first surface of the electronic component. The thermal conductive layer includes a plurality of portions spaced apart from each other.

An embodiment of the present invention provides an element transferring method that may increase a yield of transferring an element, and an electronic panel manufacturing method using the same. The element transferring method includes: preparing a carrier film in which a first surface of an element on which a terminal is formed is adhered to an adhesive surface; providing a cover adhesive layer on the adhesive surface so that the second surface of the element that is opposite to the first surface and where the terminal is not formed is covered; transferring the element to the target substrate by adhering the cover adhesive layer to the target substrate while the second surface is facing the target substrate; and separating the carrier film from the element, wherein in transferring the element, the carrier film is pressed so that the surface of the cover adhesive layer is flat at the same height as the terminal.

A manufacturing method of a package structure of an electronic device is provided. The manufacturing method includes the following. First, a carrier plate is provided. The carrier plate includes a composite structure and has a first surface and a second surface opposite to each other. Next, an anti-warpage structure is formed on the first surface of the carrier plate. Then, a redistribution structure is formed on the second surface of the carrier plate. When the package structure manufactured with the manufacturing method of the package structure of the electronic device of the disclosure is applied to the electronic device, reliability and/or electrical properties of the electronic device are enhanced.

A semiconductor device has a first semiconductor package including a substrate and an encapsulant deposited over the substrate. An adhesive tape is disposed on the encapsulant. A conductive via is formed by trench cutting through the adhesive tape and encapsulant to expose the substrate. A second semiconductor package is disposed over the adhesive tape opposite the first semiconductor package. The first semiconductor package and second semiconductor package are bonded together by the adhesive tape.

A semiconductor device includes a multi-layer board which a wiring pattern and a grounding pattern are formed. A plurality of semiconductor elements are mounted on the multi-layer board. An insulating sealing member is provided on the multi-layer board and is covering the plurality of semiconductor elements. A metal film is provided on the insulating sealing member. An in-groove metal is provided in contact with a plurality of grooves extending from a side-surface upper end of the insulating sealing member to a side-surface lower end of the multi-layer board. An in-hole metal is provided in an inner wall of a hole penetrating through the insulating sealing member and is extending to the multi-layer board. The in-hole metal is contacting with the metal film and the grounding pattern.

A semiconductor device includes a multi-layer board which a wiring pattern and a grounding pattern are formed. A plurality of semiconductor elements are mounted on the multi-layer board. An insulating sealing member is provided on the multi-layer board and is covering the plurality of semiconductor elements. A metal film is provided on the insulating sealing member. An in-groove metal is provided in contact with a plurality of grooves extending from a side-surface upper end of the insulating sealing member to a side-surface lower end of the multi-layer board. An in-hole metal is provided in an inner wall of a hole penetrating through the insulating sealing member and is extending to the multi-layer board. The in-hole metal is contacting with the metal film and the grounding pattern.