Patent classifications
H01L21/60
Electrical interconnect bridge
Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.
SEMICONDUCTOR DEVICE
A semiconductor device includes a first insulating substrate, a second insulating substrate, a first arm, a second arm connected to the first arm, and a first conductive pattern provided on the first insulating substrate. The first arm includes a plurality of first transistor chips provided on the first insulating substrate, and the second arm includes a semiconductor chip provided on the second insulating substrate. The plurality of first transistor chips are arranged adjacent to each other on the first insulating substrate, first electrodes of the plurality of first transistors are directly connected to the first conductive pattern, and each of the first electrodes is a source electrode or an emitter electrode.
SEMICONDUCTOR DEVICE
A semiconductor device includes a first insulating substrate, a second insulating substrate, a first arm, a second arm connected to the first arm, and a first conductive pattern provided on the first insulating substrate. The first arm includes a plurality of first transistor chips provided on the first insulating substrate, and the second arm includes a semiconductor chip provided on the second insulating substrate. The plurality of first transistor chips are arranged adjacent to each other on the first insulating substrate, first electrodes of the plurality of first transistors are directly connected to the first conductive pattern, and each of the first electrodes is a source electrode or an emitter electrode.
SEMICONDUCTOR DEVICE
A semiconductor device includes a first insulating substrate, a second insulating substrate, a first transistor provided on the first insulating substrate, and a first diode provided on the second insulating substrate and connected in parallel to the first transistor.
SEMICONDUCTOR DEVICE
A semiconductor device includes a first insulating substrate, a second insulating substrate, a first transistor provided on the first insulating substrate, and a first diode provided on the second insulating substrate and connected in parallel to the first transistor.
Integrated Circuit Package and Method of Forming Thereof
A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME
A semiconductor structure includes: a substrate; a first dielectric layer, located on the substrate; and a pad structure, located on the first dielectric layer. The first dielectric layer has at least one support layer. The pad structure is located above the support layer. A material strength of the support layer is greater than a material strength of the first dielectric layer.
Field device of automation technology and method for its manufacture
Disclosed is a field device of automation technology comprising a measuring transducer for ascertaining a measurement signal and a measurement transmitter for output of the measurement signal ascertained. The field device has at least one housing of the measuring transducer and/or of the measurement transmitter, in which electronic components of the measuring transducer and/or of the measurement transmitter are arranged, characterized in that the electronic components are embedded in an epoxide polymer foam, which is a reaction product of a self foaming, potting compound comprising at least the following components: 25 to 75 wt-% of a diglycidyl ether resin; at least one amine containing hardening system comprising a Mannich base; and at least one foaming agent, and a method for manufacturing a field device of automation technology.
Field device of automation technology and method for its manufacture
Disclosed is a field device of automation technology comprising a measuring transducer for ascertaining a measurement signal and a measurement transmitter for output of the measurement signal ascertained. The field device has at least one housing of the measuring transducer and/or of the measurement transmitter, in which electronic components of the measuring transducer and/or of the measurement transmitter are arranged, characterized in that the electronic components are embedded in an epoxide polymer foam, which is a reaction product of a self foaming, potting compound comprising at least the following components: 25 to 75 wt-% of a diglycidyl ether resin; at least one amine containing hardening system comprising a Mannich base; and at least one foaming agent, and a method for manufacturing a field device of automation technology.
METHOD OF MANUFACTURING AN INTERPOSER PRODUCT
A method of manufacturing an interposer product that includes: forming on a same side of an interposer substrate, by a common process, first and second portions of a gold layer, wherein the first portion of the gold layer constitutes a wire-bonding pad; depositing a Au—Sn solder on the second portion of the gold layer, the Au—Sn solder comprising a gold-tin alloy having a first composition; merging the deposited Au—Sn solder with the second portion of the gold layer by performing a reflow process to form at least one bonding bump, wherein a majority of the bonding bump is made of a eutectic composition of the gold-tin alloy, and wherein the first composition has a smaller proportion of gold than is in the eutectic composition of the gold-tin alloy; and planarizing the bonding bump to form a flat bonding bump having a selected height.