A die bonding method is disclosed, through coating bonding adhesive on front side of device wafer and bonding carrier wafer thereto, back-side connection structure can be formed on back side of device wafer to lead out an interconnect structure in device wafer to back side of device wafer, and dies thereon can be bonded at front sides to target wafer. Moreover, after device wafer is debonded from carrier wafer, the bonding adhesive is retained on front side of device wafer to provide protection to front side of device wafer during subsequent dicing of device wafer, and to avoid particles or etching by-products produced during dicing process from adhering to front side of device wafer. Such etching by-products are subsequently removed along with the bonding adhesive, ensuring cleanness of front sides of individual dies resulting from dicing process and improved quality of bonding of dies at front sides to target wafer.

A die bonding method is disclosed, through coating bonding adhesive on front side of device wafer and bonding carrier wafer thereto, back-side connection structure can be formed on back side of device wafer to lead out an interconnect structure in device wafer to back side of device wafer, and dies thereon can be bonded at front sides to target wafer. Moreover, after device wafer is debonded from carrier wafer, the bonding adhesive is retained on front side of device wafer to provide protection to front side of device wafer during subsequent dicing of device wafer, and to avoid particles or etching by-products produced during dicing process from adhering to front side of device wafer. Such etching by-products are subsequently removed along with the bonding adhesive, ensuring cleanness of front sides of individual dies resulting from dicing process and improved quality of bonding of dies at front sides to target wafer.

A circuit support structure includes a first metal layer, a second metal layer, isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer and electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to be coupled to a first integrated circuit on the circuit support structure and includes a first contact pad electrically coupled to the first circuit element. The second plurality of contact pads is adapted to be coupled to a second integrated circuit on the circuit support structure and includes a second contact pad electrically coupled to the second circuit element.

A semiconductor package includes a die pad and leads extending from the die pad. Each lead has a free end with outer surfaces extending at angles from one another. An electrically conductive plating material covers at least portions of the outer surfaces. A die attached to the die pad is electrically connected to the leads. An insulating layer extends over the leads and the die such that the free ends of the leads are exposed.

In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

The present application provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a stacked structure, the stacked structure includes a first chip and a second chip; forming a through silicon via (TSV) in the stacked structure, the TSV includes a first part and a second part communicating with the first part, a sidewall of the first part is a vertical sidewall, and a sidewall of the second part is an inclined sidewall; forming an insulating layer on the sidewall of the first part; and forming a conductive layer in the TSV.

Systems and methods are provided for monitoring wafer bonding and for detecting or determining defects in a wafer bond formed between two semiconductor wafers. A wafer bonding system includes a camera configured to monitor bonding between two semiconductor wafers. Wafer bonding defect detection circuitry receives video data from the camera, and detects a bonding defect based on the received video data.

A semiconductor package and a method for manufacturing a semiconductor package are provided. The semiconductor package includes a first semiconductor device, a second semiconductor device, and an alignment material. The first semiconductor device has a first bonding layer, and the first bonding layer includes a first bond pad contacting an organic dielectric material. The second semiconductor device has a second bonding layer, and the second bonding layer includes a second bond pad contacting the organic dielectric material. The alignment material is between the first bonding layer and the second bonding layer.

A plating-pattern plate is configured to transfer, to a substrate, a transfer pattern formed by plating. The plating-pattern plate includes a base body and transfer parts disposed on the base body. Each of the transfer parts has a transfer surface configured to have the transfer pattern to be formed on the transfer surface by plating. The transfer parts are disposed electrically independent of one another on the base body. The plating-pattern plate provides a fine conductive pattern with stable quality.