A package structure includes: a substrate; a chip arranged on a part of a surface of the substrate; a metal thermal conducting layer arranged on a top surface of the chip; a capacitive structure arranged on another part of the surface of the substrate and arranged to be independent from the chip; and a cover including a first cover layer and a second cover layer connected to the first cover layer. A first opening is defined to extend through the first and the second cover layers. The second cover layer is arranged on a bottom of the first cover layer and perpendicular to the first cover layer. The first cover layer is arranged on the capacitive structure. The chip is received in the first opening. The second cover layer is arranged between the capacitive structure and the chip, and is fixed to the substrate.

Provided is a plating film containing Au and Tl, including Tl oxides including Tl.sub.2O on a surface of the plating film, a ratio of Tl atoms constituting Tl.sub.2O to a total of Tl atoms constituting the Tl oxides and Tl atoms constituting Tl simple substances on the surface being 40% or more.

Provided is a plating film containing Au and Tl, including Tl oxides including Tl.sub.2O on a surface of the plating film, a ratio of Tl atoms constituting Tl.sub.2O to a total of Tl atoms constituting the Tl oxides and Tl atoms constituting Tl simple substances on the surface being 40% or more.

A method of plasma processing comprises generating electrons in a source chamber, generating an electric potential gradient between the source chamber and a processing chamber by applying a first negative direct current (DC) voltage to the source chamber and a ground voltage to the processing chamber, accelerating the electrons from the source chamber through a dielectric injector and into the processing chamber using the electric potential gradient, and generating an electron-beam sustained plasma (ESP) in the processing chamber using the electrons from the source chamber.

Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.

Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.

Forming a 3DIC includes providing a lower device structure comprising a first substrate with a circuit layer, providing an interconnect network layer having an interconnect structure with a first coupled to a second plurality of electrodes by connection structures on a semiconductor substrate, the first plurality of electrodes being exposed on a first surface of the interconnect layer, implanting ions through the interconnect structure to form a cleave plane in the semiconductor substrate, bonding the interconnect structure to the lower device structure so that electrodes of the first plurality of electrodes are coupled to corresponding electrodes on the lower device structure, cleaving the substrate of the bonded interconnect layer at the cleave plane, removing material from the semiconductor substrate until the second plurality of electrodes is exposed, and bonding an upper device layer to the interconnect structure.

A light detection and ranging (LIDAR) system and apparatus including a photonics chip coupled to a substrate, the photonics chip including an optical source to generate an optical beam, a waveguide to direct the optical beam through the photonics chip, a photodetector to generate an electrical signal in response to detecting a return signal, and an optical coupler to transmit the optical beam from the waveguide to a target in the field of view of the LIDAR apparatus. The system and apparatus may further include an integrated circuit (IC) chip coupled to the photonics chip, the IC chip to process the electrical signal generated by the photodetector.

A light detection and ranging (LIDAR) system and apparatus including a photonics chip coupled to a substrate, the photonics chip including an optical source to generate an optical beam, a waveguide to direct the optical beam through the photonics chip, a photodetector to generate an electrical signal in response to detecting a return signal, and an optical coupler to transmit the optical beam from the waveguide to a target in the field of view of the LIDAR apparatus. The system and apparatus may further include an integrated circuit (IC) chip coupled to the photonics chip, the IC chip to process the electrical signal generated by the photodetector.

Devices and methods that result in very low stress circuit die attachment to substrates such as PCB's and flex circuits are described. Stress, due to thermal expansion mismatches, is reduced by reducing the amount of die bonding area that is covered by adhesive material. In some instances, the area left uncovered by adhesive material may be all or partially filled with a low viscosity material that may also be thermally conductive, such as thermal grease. Reducing the contact area between the die and inherently low elasticity adhesives reduces the mechanical effect of thermal mismatches between the die and the substrate. The provided techniques are particularly beneficial when used to bond uncooled thermal imaging FPA dies to substrates.