Devices and methods that result in very low stress circuit die attachment to substrates such as PCB's and flex circuits are described. Stress, due to thermal expansion mismatches, is reduced by reducing the amount of die bonding area that is covered by adhesive material. In some instances, the area left uncovered by adhesive material may be all or partially filled with a low viscosity material that may also be thermally conductive, such as thermal grease. Reducing the contact area between the die and inherently low elasticity adhesives reduces the mechanical effect of thermal mismatches between the die and the substrate. The provided techniques are particularly beneficial when used to bond uncooled thermal imaging FPA dies to substrates.

A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.

A nucleation suppression layer including a self-assembly material can be formed on a surface of a bonding dielectric layer without depositing the self-assembly material on physically exposed surfaces of first metal bonding pads of a first semiconductor die. Metallic liners including a second metal can be formed on the physically exposed surfaces of the metal bonding pads without depositing the second metal on the nucleation suppression layer. The first semiconductor die is bonded to a second semiconductor die by inducing metal-to-metal bonding between mating pairs of the first metal bonding pads and second metal bonding pads of the second semiconductor die.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one hole slot; a position of the at least one hole slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one hole slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.

A semiconductor structure includes a first chip and a second chip. A first conductive contact pad is paced apart from a second conductive contact pad and both of the first conductive contact pad and the second conductive contact pad are connected to a first conductive connecting line. A third conductive contact pad is spaced apart from a fourth conductive contact pad and both of the third conductive contact pad and the fourth conductive contact pad are connected to a second conductive connecting line. The first conductive contact pad and the second conductive contact pad are both in staggered connection with the third conductive contact pad, and the first conductive contact pad and the second conductive contact pad are both in staggered connection with the fourth conductive contact pad.

The present disclosure provides an antenna packaging structure radiating electromagnetic waves in a horizontal direction parallel to the device plane and a method making the same. The method includes: providing a support substrate, and forming a separation layer; forming a rewiring layer on the separation layer; forming an antenna array layer on the rewiring layer, the antenna array layer is electrically connected to the metal wire layer; the antenna array layer includes a plurality of antennas which radiates e-m waves in a horizontal direction; each antennas comprises first metal sheets extending along a first direction and second metal sheets extending along a second direction, the first metal sheets are arranged with sheets in parallel and spaced by an sheet-to-sheet interval, second metal sheets are arranged with sheets in parallel and spaced by an sheet-to-sheet interval; forming a molding material layer, which molds the antenna array layer.

The present disclosure provides an antenna packaging structure radiating electromagnetic waves in a horizontal direction parallel to the device plane and a method making the same. The method includes: providing a support substrate, and forming a separation layer; forming a rewiring layer on the separation layer; forming an antenna array layer on the rewiring layer, the antenna array layer is electrically connected to the metal wire layer; the antenna array layer includes a plurality of antennas which radiates e-m waves in a horizontal direction; each antennas comprises first metal sheets extending along a first direction and second metal sheets extending along a second direction, the first metal sheets are arranged with sheets in parallel and spaced by an sheet-to-sheet interval, second metal sheets are arranged with sheets in parallel and spaced by an sheet-to-sheet interval; forming a molding material layer, which molds the antenna array layer.

The present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a die and a first adhesive layer; a surface of the substrate is provided with an insulation layer; the die is arranged on a surface of the insulation layer via the first adhesive layer; the insulation layer is provided with at least one slot; a position of the at least one slot corresponds to at least a part of an edge of the first adhesive layer; a second adhesive layer is arranged in the at least one slot; at least a part of a surface of the second adhesive layer is connected with the first adhesive layer; and an elasticity modulus of the second adhesive layer is smaller than an elasticity modulus of the first adhesive layer.

A method of forming an integrated circuit package includes attaching a first die to an interposer. The interposer includes a first die connector and a second die connector on the interposer and a first dielectric layer covering at least one sidewall of the first die connector and at least one sidewall of the second die connector. The first die is coupled to the first die connector and to the first dielectric layer and the second die connector is exposed by the first die. The method further includes recessing the first dielectric layer to expose at least one sidewall of the second die connector and attaching a second die to the interposer, the second die being coupled to the second die connector.

The invention relates to a method for manufacturing (S) an electronic board (1) comprising the following steps: forming (S1, S4) a cavity (20) in the conductive skin layer (C.sub.1) and in an underlying insulating layer (10), so that at least part of a solder pad (4) is exposed, filling (S5) the cavity (20) with a solder paste (24), placing (S6) an SMD (3) opposite the cavity (20), soldering the SMD (3) on the electronic board (1).