An electronic device includes a substrate having contact pads disposed thereon and traces interconnecting the contact pads. A first integrated circuit (IC) die is mounted on the substrate and includes a predefined set of circuit components arranged on the first IC die in a first geometrical pattern, which is non-symmetrical under reflection about a given axis in a plane of the die. A second IC die is mounted on the substrate and includes the predefined set of circuit components arranged on the second IC die in a second geometrical pattern, which is a mirror image of the first geometrical pattern with respect to the given axis.

An arrangement apparatus includes a stage, an arrangement part, and a control part. The stage supports a substrate. The arrangement part holds a die and arranges multiple dies on the substrate supported by the stage. The control part has a map data indicating arrangement positions of the dies and generated based on a positional relationship among patterns formed by an exposure apparatus, and controls, based on the map data, relative positions between the stage and the arrangement part when arranging the dies on the substrate.

A semiconductor device manufacturing device (10) includes a stage (12), an installing head (14) that has a chip holding surface (26) and disposes a chip (100) on a substrate (110), a measuring mechanism (16) that measures a tilt angle of the chip (100) loaded on an installing surface (112) of the substrate (110) by the installing head (14) with respect to the installing surface (112) as a detection tilt angle Sd, a holding surface adjusting mechanism (18) that changes a holding surface tilt angle Sb which is a tilt angle of the chip holding surface (26) with respect to a loading surface (21), and a controller (20) that calculates a correction amount C of the holding surface tilt angle Sb based on the detection tilt angle Sd and changes the holding surface tilt angle Sb by the holding surface adjusting mechanism (18) according to the calculated correction amount C.

The present disclosure provides a semiconductor structure and a forming method thereof. The semiconductor structure includes: a substrate, including a first side and a second side opposite to each other; a dielectric layer, provided at the first side of the substrate; a first through silicon via (TSV) structure, extending from a top surface of the dielectric layer to the first side of the substrate; and a second TSV structure, extending from the second side of the substrate to the first side of the substrate, coming into contact with the first TSV structure at the first side of the substrate, and having a preset opening width.

A semiconductor die is arranged on a substrate and an encapsulation of laser direct structuring (LDS) material is molded onto the semiconductor die. A through mold via (TMV) extends through the encapsulation. This TMV includes a collar section that extends through a first portion of the encapsulation from an outer surface to an intermediate level of the encapsulation, and a frusto-conical section that extends from a bottom of the collar section through a second portion of the encapsulation. The collar section has a first cross-sectional area at the intermediate level. The first end of the frusto-conical section has a second cross-section area at the intermediate level. The second cross-sectional area is smaller than the first cross-sectional area. The TMV can have an aspect ratio which is not limited to 1:1.

A semiconductor die is arranged on a substrate and an encapsulation of laser direct structuring (LDS) material is molded onto the semiconductor die. A through mold via (TMV) extends through the encapsulation. This TMV includes a collar section that extends through a first portion of the encapsulation from an outer surface to an intermediate level of the encapsulation, and a frusto-conical section that extends from a bottom of the collar section through a second portion of the encapsulation. The collar section has a first cross-sectional area at the intermediate level. The first end of the frusto-conical section has a second cross-section area at the intermediate level. The second cross-sectional area is smaller than the first cross-sectional area. The TMV can have an aspect ratio which is not limited to 1:1.

A semiconductor device includes a plurality of storage elements formed on conductive structures and a cap layer located over the storage elements and the conductive structures. It further includes an interlevel dielectric (ILD) layer over the cap layer, where the ILD layer comprises trenches reaching a top portion of the storage elements, and via openings. The device also has a conductive material formed in the trenches and the via openings, where the conductive material makes contact with the storage elements and forms interlevel vias in the via openings.

To provide a semiconductor device regarding which filling material can be suitably filled in between substrates in a case of disposing a plurality of component parts of the semiconductor device between the substrates, and a manufacturing method of the same. A semiconductor device according to the present disclosure includes a first substrate, a plurality of protruding portions that protrude with respect to a first face of the first substrate, a plurality of types of insulating films that are provided at least between the protruding portions on the first face of the first substrate, a second substrate that is provided facing the first face of the first substrate, and a filling material that is provided between the first substrate and the second substrate, so as to come into contact with the plurality of types of insulating films.

To provide a semiconductor device regarding which filling material can be suitably filled in between substrates in a case of disposing a plurality of component parts of the semiconductor device between the substrates, and a manufacturing method of the same. A semiconductor device according to the present disclosure includes a first substrate, a plurality of protruding portions that protrude with respect to a first face of the first substrate, a plurality of types of insulating films that are provided at least between the protruding portions on the first face of the first substrate, a second substrate that is provided facing the first face of the first substrate, and a filling material that is provided between the first substrate and the second substrate, so as to come into contact with the plurality of types of insulating films.

Disclosed is a semiconductor package comprising a semiconductor chip, an external connection member on the semiconductor chip, and a dielectric film between the semiconductor chip and the external connection member. The semiconductor chip includes a substrate, a front-end-of-line structure on the substrate, and a back-end-of-line structure on the front-end-of-line structure. The back-end-of-line structure includes metal layers stacked on the front-end-of-line structure, a first dielectric layer on the uppermost metal layer and including a contact hole that vertically overlaps a pad of an uppermost metal layer, a redistribution line on the first dielectric layer and including a contact part in the contact hole and electrically connected to the pad, a pad part, and a line part that electrically connects the contact part to the pad part, and an upper dielectric layer on the redistribution line.