Patent classifications
H01L21/67121
Packaged wafer manufacturing method and device chip manufacturing method
Disclosed herein is a packaged wafer manufacturing method including the steps of forming a groove along each division line on the front side of a wafer, each groove having a depth greater than the finished thickness of the wafer, next removing a chamfered portion from the outer circumference of the wafer to thereby form a step portion having a depth greater than the depth of each groove, next setting a die of a molding apparatus on the bottom surface of the step portion of the wafer in the condition where a space is defined between the die and the wafer, and next filling a mold resin into this space. Accordingly, the device area of the wafer is covered with the mold resin and each groove of the wafer is filled with the mold resin to thereby obtain a packaged wafer.
Diodes offering asymmetric stability during fluidic assembly
Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate.
PROCESSING DEVICE AND METHOD OF MANUFACTURING DISPLAY DEVICE
According to one embodiment, a processing device includes a stage, a support member including a movable support block, and a vacuum device including a main body and a block, and the processing moves the support block in a first direction to support an end portion region of a display panel and a flexible wiring board disposed outside the stage, causes the end portion area of the display panel and the flexible wiring board to be adsorbed to the main body of the vacuum device, and rotates the main body of the vacuum device and the block of the vacuum device by 180 to bend the display panel in a bend area of the end portion region.
System and method for mitigating overlay distortion patterns caused by a wafer bonding tool
A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.
Manufacturing method of semiconductor package using jig
A jig for manufacturing a semiconductor package includes a bottom piece and an upper piece. The bottom piece includes a base, a support plate, and at least one elastic connector. The support plate is located in a central region of the base. The at least one elastic connector is interposed between the support plate and the base. The upper piece includes a cap and outer flanges. The cap overlays the support plate when the upper piece is disposed on the bottom piece. The outer flanges are disposed at edges of the cap, connected with the cap. The outer flanges contact the base of the bottom piece when the upper piece is disposed on the bottom piece. The cap includes an opening which is a through hole. When the upper piece is disposed on the bottom piece, a vertical projection of the opening falls entirely on the support plate.
Method of fabricating package
A method of fabrication a package and a stencil structure are provided. The stencil structure includes a first carrier having a groove and stencil units placed in the groove of the first carrier. At least one of the stencil units is slidably disposed along sidewalls of another stencil unit. Each of the stencil units has openings.
APPARATUS FOR PACKAGING LIQUID CRYSTAL GLASS SUBSTRATES
The present invention discloses an apparatus for packaging liquid crystal glass substrates, comprising multiple housings, a cover and a unit forming member, wherein the multiple housings are overlapped together in vertical direction, the cover covers the topmost housing of the multiple housings, each housing comprises a cavity for receiving a liquid crystal glass substrate, the unit forming member is configured to clamp at least two housings of the multiple housings together as a housing unit, the unit forming member comprises at least one clamp. According to the present invention, even when there are many layers of housings, the centre of gravity of housings can be align with each other, and the risk of overturning can be avoided.
Open cavity plastic package
A method for manufacturing open cavity integrated circuit packages, the method comprising: placing a wire-bound integrated circuit in a mold; forcing a pin to contact a die of the wire-bound integrated circuit by applying a force between the pin and the mold; injecting plastic into the mold; allowing the plastic to set around the integrated circuit to form a package having an open cavity defined by the pin; and removing the open cavity integrated circuit package from the mold. A mold for forming a package for an integrated circuit sensor device, comprising: a bottom part for supporting an integrated circuit die; a top part that is operable to be placed on top of said bottom part to form a cavity into which a plastic material can be injected to form the package, wherein the top part of the mold comprises a spring-loaded pin arrangement comprising a cover that covers a sensor area on the integrated circuit die and provides for an opening when the plastic material is injected.
Coating of graphite tooling for manufacture of semiconductors
A tool useful in the manufacture of a semiconductor is disclosed. A mold is providing having an interior defining a planar capillary space. A coating substantially covers at least the planar capillary space of the graphite member. The coating is substantially non-reactive to silicon at temperatures greater than approximately 1420 degrees Centigrade.
SYSTEM AND METHOD FOR MITIGATING OVERLAY DISTORTION PATTERNS CAUSED BY A WAFER BONDING TOOL
A system includes a wafer shape metrology sub-system configured to perform one or more shape measurements on post-bonding pairs of wafers. The system includes a controller communicatively coupled to the wafer shape metrology sub-system. The controller receives a set of measured distortion patterns. The controller applies a bonder control model to the measured distortion patterns to determine a set of overlay distortion signatures. The bonder control model is made up of a set of orthogonal wafer signatures that represent the achievable adjustments. The controller determines whether the set of overlay distortion signatures associated with the measured distortion patterns are outside tolerance limits provides one or more feedback adjustments to the bonder tool.