A method for joining a microelectronic chip to at least one wire element comprises a first step of applying a cover to a first face of the microelectronic chip, the cover being configured to form, with the first face, at least one temporary side groove. The method additionally comprises a step of inserting the wire element into the temporary groove. The method further comprises a step of attaching the wire element to the microelectronic chip. The method additionally comprises a step of removing the cover from the microelectronic chip.

A method of forming an integrated circuit includes: forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer; and patterning the photoresist layer to form a via mask, where the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer. The method further includes: etching the film layer and the dielectric layer based on the patterned photoresist layer; ashing the photoresist layer and the film layer; etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region; etching the hard mask layer and the dielectric layer; and performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

Embodiments relate to using photocurable polymers to place light emitting diodes (LEDs) onto an electronic display substrate after fabrication of the LEDs. A LED assembly system places LEDs on a temporary substrate after fabrication and applies a a photocurable polymer onto the top surfaces of the LEDs. A transparent pickup head aligns with a subset of the LEDs. The pickup head is positioned on the top surfaces of the subset of LEDs such that the layer of the photocurable polymer is in between the pickup head and the top surface of the subset of the LEDs. Light is directed through the pickup head to cure the photocurable polymer, adhering the subset of LEDs to the pickup head. The subset of LEDs is removed away from the temporary substrate, due to relative movement between the temporary substrate and the pickup head.

A positioning table, for example for a wire bonder has first and second arms, each of said first and second arms being independently drivable linearly along a first axis, and a stage that is engaged with both the first and second arms. The stage engages with each of the first and second arms via a respective engagement mechanism such that the stage is movable both linearly along the first axis, and rotatable about a rotary axis coincident with a center-point of the stage, the rotary axis being orthogonal to the first axis. Each engagement mechanism is configured to permit a respective distance between the center-point of the stage and an end of each of the first and second arms to vary during movement of an arm along the first axis.

An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

A wire bonding apparatus according to an embodiment bonds a wire to a bonding portion by generating an ultrasonic vibration in a state of pressing the wire onto the bonding portion. The wire bonding apparatus includes a bonding tool that causes the wire to contact the bonding portion and applies a load, an ultrasonic horn that generates the ultrasonic vibration, a load sensor that continuously detects the load applied from the bonding tool to the bonding portion, and a controller that controls the operation of the bonding tool and the ultrasonic horn. The controller analyzes data of the load output from the load sensor between when the wire contacts the bonding portion and when the ultrasonic vibration is generated, and controls the operation of the bonding tool and the ultrasonic horn based on an analysis result.

A semiconductor device including a multilayer wiring layer comprising a first wiring, a first insulating film formed on the multilayer wiring layer and having a first opening exposing a portion of the first wiring, a second insulating film formed on the first insulating film and having a second opening continuing with the first opening, and an inductor formed of the first wiring, and a second wiring electrically connected with the first wiring through a via formed in the first opening. A side surface of the via contacts with the first insulating film, and does not contact with the second insulating film.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

The present disclosure provides a chip transfer substrate, a chip transfer device and a chip transfer method. The chip transfer substrate includes a substrate, a plurality of bases spaced apart from each other on the substrate, the plurality of bases being configured to carry micro light emitting diodes (Micro LEDs) to be transferred and being movable on the substrate; and a plurality of distance adjusting components each arranged between two adjacent bases and configured to adjust a distance between the two adjacent bases.