An inertial sensor includes: a substrate; an insulating film provided on a main surface of the substrate; a first semiconductor layer and a second semiconductor layer which are provided on an opposite-side surface of the insulating film from the substrate; a first oxide film provided on a first side surface of the first semiconductor layer on a second semiconductor layer side; a second oxide film provided on a second side surface of the second semiconductor layer on a first semiconductor layer side; a planarization insulating film provided above the first oxide film and the second oxide film and between the first oxide film and the second oxide film; and a wiring provided on the planarization insulating film and electrically coupled to the second semiconductor layer.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.

A method for joining a microelectronic chip to at least one wire element comprises: a first step of applying a cover to a first face of the microelectronic chip, the cover being configured to form, with the first face, at least one temporary side groove; a step of inserting the wire element into the temporary groove; a step of attaching the wire element to the microelectronic chip; and a step of removing the cover from the microelectronic chip.

A method for manufacturing electronic apparatus includes: a step (A) of preparing a structure provided with an adhesive film and at least one electronic component affixed to an adhesive surface of the adhesive film; a step (B) of disposing the structure in an electronic component testing apparatus such that the electronic component is positioned over an electronic component installation region of a sample stand with the adhesive film interposed between the electronic component and the electronic component installation region, the electronic component testing apparatus being provided with a probe card at a position facing the sample stand and includes a probe terminal; a step (C) of evaluating the properties of the electronic component while being affixed to the adhesive film with the probe terminal being in contact with a terminal of the electronic component; and a subsequent step (D) of picking up the electronic component from the adhesive film.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

The present invention is provided with: first and second bases, which are guided by a guide rail to thereby linearly move; a linear scale provided with graduations at predetermined pitches in the moving direction; and first and second encoder heads attached to the first and second bases. In the present invention, while maintaining, at a predetermined interval a, a distance between the first and second encoder heads, and moving the first and second bases along the guide rail, first and second graduation numbers, at which the first and second encoder heads are positioned, are sequentially detected from the first and second encoder heads, and the amount of movement of the first and second bases is controlled on the basis of the ratio between the predetermined interval a and the distance on the scale between the first graduation numbers and the second graduation numbers.

An apparatus for attaching an interconnector of a solar cell panel, includes an interconnector supply unit for unwinding the interconnector wound around a winding roll and moving the interconnector in a processing direction; and an attachment unit for attaching the interconnector to a solar cell, wherein the interconnector supply unit includes the winding roll, around which the interconnector is wound; and an unwinding control member for unwinding the interconnector from the winding roll, and wherein the unwinding control member allows the interconnector to be unwound so as to pass through one end of the winding roll in a longitudinal direction.

A wire bonding apparatus includes: a first tensioner which forms, nearer a wire supply side than a bonding tool, a first gas flow for applying a tension toward the wire supply side on a wire; a second tensioner which forms, between the first tensioner and a pressing part of the bonding tool, a second gas flow for applying a tension toward the wire supply side on the wire; and a control part which controls the first tensioner and the second tensioner. The control part implements control, in a predetermined period after a first bonding step for bonding the wire to a first bonding point, to turn off at least the second gas flow of the second tensioner among the first tensioner and the second tensioner or to make at least the second gas flow smaller than in the first bonding step.

Methods disclosed herein include scanning a focus spot formed by a laser beam over either a metal layer or IC structures that include a metal and a non-metal. The focus spot is scanned over a scan path that includes scan path segments that partially overlap. The focus spot has an irradiance and a dwell time selected to locally melt the metal layer or locally melt the metal of the IC structures without melting the non-metal. This results in rapid melting and recrystallization of the metal, which decreases the resistivity of the metal and results in improved performance of the IC chips being fabricated. Also disclosed is an example laser melt system for carrying out methods disclosed herein is also disclosed.