Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a Ni.sub.xSi.sub.1-x layer on the substrate, where x is between about 0.01 and about 0.99.

An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

A method of forming an integrated circuit includes: forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer; and patterning the photoresist layer to form a via mask, where the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer. The method further includes: etching the film layer and the dielectric layer based on the patterned photoresist layer; ashing the photoresist layer and the film layer; etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region; etching the hard mask layer and the dielectric layer; and performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.

A device for attaching conductive balls to a substrate includes a first plate, a second plate and a controller. The first plate includes first recesses. Each of the first recesses picks up a corresponding conductive ball to be attached to the semiconductor package. The second plate includes second recesses. Each of the second recesses picks up a corresponding conductive ball to be attached to the semiconductor package. The first plate and the second plate are separated from each other. The controller controls each of the first plate and the second plate to be separately moved up or down so that a lower surface of the first plate and a lower surface of the second plate are positioned differently in a first direction normal the lower surface of the first plate.

A positioning table, for example for a wire bonder has first and second arms, each of said first and second arms being independently drivable linearly along a first axis, and a stage that is engaged with both the first and second arms. The stage engages with each of the first and second arms via a respective engagement mechanism such that the stage is movable both linearly along the first axis, and rotatable about a rotary axis coincident with a center-point of the stage, the rotary axis being orthogonal to the first axis. Each engagement mechanism is configured to permit a respective distance between the center-point of the stage and an end of each of the first and second arms to vary during movement of an arm along the first axis.

A bonding apparatus 10 having a diagonal optical system 30, the bonding apparatus moves a capillary 24 down to a first heightwise position to calculate a position A11 of a tip end portion of the capillary 24 and a position A12 of a tip end portion of the capillary in an image on an imaging plane of the diagonal optical system 30, and similarly moves the capillary 24 down to a further lower second heightwise position to calculate a position A21 of the tip end portion of the capillary 24 and a position A22 of the tip end portion of the capillary in the image on the imaging plane. The bonding apparatus then estimates the position of the landing point of the capillary 24 on a bonding target 8 based on positional data for the four calculated positions A11, A12, A21, and A22, the first heightwise position, and the second heightwise position. With this, it is possible to use the diagonal optical system in the bonding apparatus to further improve positional accuracy in the bonding process.

Disclosed is a method for attaching an interconnector of a solar cell panel, including moving the interconnector, unwound from a winding roll, in a processing direction, and attaching the interconnector to a solar cell. In the moving, the interconnector, which is wound around the winding roll, is unwound so as to pass through one end of the winding roll in a longitudinal direction.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

An integrated circuit including a first standard cell including, first transistors, the first transistors being first unfolded transistors, a first metal pin, a second metal pin, and a third metal pin on a first layer, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween less than or equal to 80 nm, a fourth metal pin and a fifth metal pin at a second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction, a first via between the first metal pin and the fourth metal pin, and a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch.

Methods and apparatus to form fully self-aligned vias are described. First conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed first conductive lines and pillars are formed from the first metal film. Some of the pillars are selectively removed and a second insulating layer is deposited around the remaining pillar. The remaining pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.