A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.

An apparatus and method for providing an artificial standoff to the bottom of leads on a QFN device sufficient to provide a gap that changes the fluid dynamics of solder flow and create a unique capillary effect that drives solder up the of leads of a UN device when it is attached to a printed wiring board (PWB).

Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a Ni.sub.xSi.sub.1-x layer on the substrate, where x is between about 0.01 and about 0.99.

A first metallization layer comprises a set of first conductive lines that extend along a first direction on a first dielectric layer on a substrate. Pillars are formed on recessed first dielectric layers and a second dielectric layer covers the pillars. A dual damascene etch provides a contact hole through the second dielectric layer and an etch removes the pillars to form air gaps.

An electronic apparatus includes: an electronic module; a display panel disposed on the electronic module and including a first display region and a second display region adjacent to the first display region, the second display region overlapping the electronic module; and a polarization plate disposed on the display panel and including a first polarization region overlapping the first display region and a second polarization region including a polarization part and a non-polarization part having higher light transmittance than the polarization part, the non-polarization part overlapping the second display region.

A method of forming a semiconductor device includes forming a tungsten layer over a semiconductor substrate in a first chamber, transferring the substrate over which the tungsten layer is formed from the first chamber to a second chamber without exposing into an atmosphere including oxygen, and forming a silicon nitride layer on the tungsten layer in the second chamber.

A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.

A method for manufacturing electronic apparatus includes: a step (A) of preparing a structure provided with an adhesive film and at least one electronic component affixed to an adhesive surface of the adhesive film; a step (B) of disposing the structure in an electronic component testing apparatus such that the electronic component is positioned over an electronic component installation region of a sample stand with the adhesive film interposed between the electronic component and the electronic component installation region, the electronic component testing apparatus being provided with a probe card at a position facing the sample stand and includes a probe terminal; a step (C) of evaluating the properties of the electronic component while being affixed to the adhesive film with the probe terminal being in contact with a terminal of the electronic component; and a subsequent step (D) of picking up the electronic component from the adhesive film.

A method and an apparatus for processing a peripheral portion of a substrate, such as a wafer, are disclosed. The substrate processing method includes: holding a substrate on a substrate stage; rotating the substrate stage and the substrate about an axis of the substrate stage; directing a laser beam to an edge portion of the rotating substrate to form an annular crack in the substrate; and pressing a polishing tool against the edge portion of the rotating substrate to form a stepped recess in a peripheral portion of the substrate.

A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.