Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a Ni.sub.xSi.sub.1-x layer on the substrate, where x is between about 0.01 and about 0.99.

The disclosure is and includes at least an apparatus, system and method for a ramped electrical interconnection for use in semiconductor fabrications. The apparatus, system and method includes at least a first semiconductor substrate having thereon a first electrical circuit comprising first electrical components; a second semiconductor substrate at least partially covering the first electrical circuit, and having thereon a second electrical circuit comprising second electrical components; a ramp formed through the second semiconductor substrate between at least one of the first electrical components and at least one of the second electrical components; and an additively manufactured conductive trace formed on the ramp to electrically connect the at least one first electrical component and the at least one second electrical component.

To provide a method for removing an organic cured film on a substrate, which can satisfactorily remove the organic cured film formed on the substrate while suppressing damage on a wiring material such as copper, and an acidic cleaning liquid which can be preferably used in the method. When removing an organic cured film on a substrate, the organic cured film is contacted with an acidic cleaning liquid, and an acidic cleaning liquid, which includes sulfuric acid and a water-soluble organic solvent and does not include a compound capable of generating nitronium ions, the content of water being 5% by mass or less, is used as the acidic cleaning liquid.

Provided are an apparatus for manufacturing a semiconductor device and a method of manufacturing a semiconductor package using the same. The manufacturing apparatus may include a base with a plurality of through holes and weight blocks respectively bound by the through holes.

A method and a computing system, for manufacturing a three-dimensional semiconductor device including first and second semiconductor device layers, are provided. The method includes: identifying candidate locations in a via area of the first semiconductor layer; identifying nets of the second semiconductor layer to be connected to through-via structures corresponding to the candidate locations; identifying a plurality of connection costs respectively corresponding to connections between the through-via structures and the nets; identifying pairs of the nets and the through-via structures, based on the plurality of connection costs; allocating the through-via structures according to the pairs; forming the through-via structures at the candidate locations; and forming electrical connections between the through-via structures.

Disclosed are pre-wetting apparatus designs and methods. In some embodiments, a pre-wetting apparatus includes a degasser, a process chamber, and a controller. The process chamber includes a wafer holder configured to hold a wafer substrate, a vacuum port configured to allow formation of a subatmospheric pressure in the process chamber, and a fluid inlet coupled to the degasser and configured to deliver a degassed pre-wetting fluid onto the wafer substrate at a velocity of at least about 7 meters per second whereby particles on the wafer substrate are dislodged and at a flow rate whereby dislodged particles are removed from the wafer substrate. The controller includes program instructions for forming a wetting layer on the wafer substrate in the process chamber by contacting the wafer substrate with the degassed pre-wetting fluid admitted through the fluid inlet at a flow rate of at least about 0.4 liters per minute.

Disclosed is a manufacturing apparatus of a light-emitting element. The manufacturing apparatus includes: a main transporting route including a first transfer device and a second transfer device connected to each other through a first transporting chamber; a sub-transporting route extending in a direction intersecting the main transporting route, the sub-transporting route including: a second transporting chamber connected to the first transfer device or the second transfer device; and a delivery chamber connected to the second transporting chamber; and a plurality of treatment chambers connected to the delivery chamber. A region to which the first transfer device, the second transfer device, the first transporting chamber, and the second transporting chamber are connected is under a continuous vacuum environment.

A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.

A wire bonding system according to the present invention comprises: an acquisition unit that acquires information pertaining to the diameter of a pressure-bonded ball where a wire is pressure-bonded to an electronic component by wire bonding; a first storage unit that stores the information pertaining to the pressure-bonded ball diameter which has been acquired by the acquisition unit; and an inspection unit that inspects the quality of wire bonding on the basis of the information pertaining to the pressure-bonded ball diameter which has been read from the first storage unit. With the wire bonding system, it is possible to enhance convenience in a method for checking the quality of wire bonding.

A soldering apparatus as a conveyance apparatus includes a substrate loading portion to load a substrate on the soldering apparatus, an intermittent feeding unit to intermittently feed the substrate loaded on the soldering apparatus, a substrate discharge portion to discharge the intermittently fed substrate to the outside of the soldering apparatus and a controller to control conveyance of the substrate. The substrate loading portion includes a first conveyance path to convey the substrate, a first sensor provided in the vicinity of a substrate loading inlet of the substrate loading portion, and a second sensor arranged in a downstream side of the first sensor along the substrate conveyance direction. The intermittent feeding unit includes a second conveyance path for conveying the substrate, and a third sensor placed in the vicinity of an upstream end of the intermittent feeding unit along the substrate conveyance direction.