H01L21/67282

TRANSPARENT SUBSTRATE WITH LIGHT BLOCKING EDGE EXCLUSION ZONE
20200219819 · 2020-07-09 ·

Embodiments of the present disclosure generally relate to an optically transparent substrate, comprising a major surface having a peripheral edge region with an orientation feature formed therein, and a texture formed on the peripheral edge region, the texture having an opacity that is greater than an opacity of the major surface.

LASER MARKING DEVICE AND LASER MARKING METHOD

A laser marking device includes a laser emission unit configured to emit a laser beam to a first surface of an object to be processed, and a pressing unit configured to press a second surface that is opposite to the first surface of the object to be processed to make the first surface of the object to be flat. The pressing unit includes a first pressing portion configured to press an edge area of the second surface in a contact manner, and at least one second pressing portion configured to press a middle area of the second surface in a non-contact manner to maintain a separation distance from the second surface within a certain distance.

HIGH REGISTRATION PARTICLES-TRANSFERRING SYSTEM

Disclosed herein are implementations of a particles-transferring system, particle transferring unit, and method of transferring particles in a pattern. In one implementation, a particles-transferring system includes a first substrate including a first surface to support particles in a pattern, particle transferring unit including an outer surface to be offset from the first surface by a first gap, and second substrate including a second surface to be offset from the outer surface by a second gap. The particle transferring unit removes the particles from the first surface in response to the particles being within the first gap, secures the particles in the pattern to the outer surface, and transports the particles in the pattern. The second substrate removes the particles in the pattern from the particle transferring unit in response to the particles being within the second gap. The particles are to be secured in the pattern to the second surface.

ALIGNMENT MARK AND SEMICONDUCTOR DEVICE, AND FABRICATION METHODS THEREOF
20200161251 · 2020-05-21 ·

An alignment mark, a semiconductor device, and fabrication methods of the alignment mark and the semiconductor device are provided. The method includes providing a first base substrate, and forming a plurality of alignment marks on the first base substrate. The method also includes dicing the first base substrate to form a plurality of alignment dies. Each alignment die includes a diced first base substrate and at least one alignment mark diced from the plurality of alignment marks on the diced first base substrate. In addition, the method includes providing a second base substrate for aligning, and forming a bonding film on the second base substrate. Further, the method includes attaching an alignment die of the plurality of alignment dies to the bonding film on an alignment region of the second base substrate using a die attach process.

Using identifiers to map edge ring part numbers onto slot numbers

Methods and systems for tracking an edge ring includes capturing an edge ring identifier from a source related to the edge ring. The edge ring is inserted into a slot of an edge ring carrier, wherein the edge ring is being assigned to the edge ring carrier. The edge ring identifier is tracked to determine transfers into and out of the edge ring carrier and into and out of a processing station. The tracking of the edge ring identifier builds a metadata file that provides lifetime information regarding the edge ring.

Wafer table with dynamic support pins

A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.

INTEGRATED CIRCUIT SECURITY
20200144203 · 2020-05-07 ·

Verifying a product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the product.

Wafer Table with Dynamic Support Pins
20200126839 · 2020-04-23 ·

A method for semiconductor fabrication includes mounting a wafer onto a first wafer table. The first wafer table includes a first set of pins that support the wafer, the first set of pins having a first pitch between adjacent pins. The method further includes forming a first set of overlay marks on the wafer; and transferring the wafer onto a second wafer table. The second wafer table includes a second set of pins having a second pitch between adjacent pins. The second set of pins are individually and vertically movable, and the second pitch is smaller than the first pitch. The method further includes moving a portion of the second set of pins such that a remaining portion of the second set of pins supports the wafer and the remaining portion has the first pitch between adjacent pins.

Wafer processing system
10629462 · 2020-04-21 · ·

A wafer processing system includes a laser processing apparatus, a grinding apparatus, a tape sticking apparatus, a first cassette placement part, a second cassette placement part, a conveying unit that conveys a wafer, and a controller that controls the respective constituent elements. The controller includes a first processing program instructing section that conveys a wafer unloaded from a first cassette in order of the laser processing apparatus, the grinding apparatus, the tape sticking apparatus, and a second cassette and sequentially carries out processing by each apparatus for the one wafer, and a second processing program instructing section that conveys the wafer unloaded from the first cassette in order of the grinding apparatus, the laser processing apparatus, the tape sticking apparatus, and the second cassette and sequentially carries out processing by each apparatus for the one wafer.

Method of manufacturing semiconductor package

A method of manufacturing a semiconductor package includes obtaining a plurality of individual chips classified according to a test bin item as a result of performing an electrical die sorting (EDS) process including testing electrical characteristics of a plurality of chips at a wafer level, packaging the individual chips on corresponding chip mounting regions of a circuit substrate and forming a plurality of individual packages based on position information of the chip mounting regions, each of the individual packages having test bin item information corresponding to the test bin item, classifying the plurality of individual packages according to the test bin item based on the test bin item information, and testing the individual packages classified according to the test bin item.