H01L21/67288

Detecting damaged semiconductor wafers utilizing a semiconductor wafer sorter tool of an automated materials handling system

A device may detect a semiconductor wafer to be transferred from a source wafer carrier to a target wafer carrier, and may cause a light source to illuminate the semiconductor wafer. The device may cause a camera to capture images of the semiconductor wafer after the light source illuminates the semiconductor wafer, and may perform image recognition of the images of the semiconductor wafer to determine whether an edge of the semiconductor wafer is damaged. The device may cause the semiconductor wafer to be provided to the source wafer carrier when the edge of the semiconductor wafer is determined to be damaged, and may cause the semiconductor wafer to be provided to the target wafer carrier when the edge of the semiconductor wafer is determined to be undamaged.

SUCTION CLAMP, OBJECT HANDLER, STAGE APPARATUS AND LITHOGRAPHIC APPARATUS
20230121922 · 2023-04-20 · ·

A suction clamp for clamping an object. The suction clamp includes a base structure including a base and a connection area, and a first pad for receiving the object. The suction clamp further includes a resilient member connecting the first pad to the connection area of the base structure such that the first pad is moveable relative to the base between a receiving position for receiving the object and a clamping position for clamping the object, wherein the resilient member is adapted to bias the first pad to the receiving position. The suction clamp further includes a suction opening arranged in the base and adapted to be connected to a suction device for providing a suction force for clamping the object on the first pad.

METHOD FOR MEASURING DIC DEFECT SHAPE ON SILICON WAFER AND POLISHING METHOD
20230125000 · 2023-04-20 · ·

A method for measuring a DIC defect shape on a silicon wafer, the method including steps of: detecting a DIC defect on a main surface of the silicon wafer with a particle counter; specifying position coordinates of the detected DIC defect; and measuring a shape including at least a height or depth of the detected DIC defect by utilizing the specified position coordinates according to phase-shifting interferometry. The method for measuring a DIC defect shape by which the shape including size of DIC defect generated on a main surface of a silicon wafer is easily and precisely measured.

HIGH PRECISION VPD-DC SCAN
20230118379 · 2023-04-20 · ·

The invention relates to a method and system for performing VPD-DC on wafer surfaces, wherein the pipette substitutes for the function of the scan tube and is operated such that a bulge of scanning liquid protrudes from the pipette channel and contacts the wafer surface for scanning.

SUBSTRATE TREATING APPARATUS AND METHOD FOR VERIFYING ERROR OF FLOW METER USING THE SAME
20230120764 · 2023-04-20 · ·

The inventive concept provides a substrate treating apparatus. The substrate treating apparatus includes a housing having a treating space for treating a substrate therein; a support unit configured to support the substrate at the treating space; a nozzle for supplying a liquid to the substrate placed on the support unit; a liquid supply unit configured to supply the liquid to the nozzle and have a flow meter; and a flow rate measuring unit configured to verify an error of the flow meter; and a controller for controlling the liquid supply unit and the flow rate measuring unit, and wherein the flow rate measuring unit comprises: a cup for accommodating the liquid; a measuring means configured to verify a level of the liquid accommodated in the cup; and a discharge line for discharging the liquid within the cup and having a discharge valve installed thereon, and wherein the controller controls the liquid supply unit to discharge a liquid of a first amount to the cup for a first time in a state at which the discharge valve is closed, and controls the measuring means to determine whether an error has occurred in the flow meter by determining whether the level of the liquid accommodated in the cup is the first amount.

INSPECTION SYSTEM OF SEMICONDUCTOR WAFER AND METHOD OF DRIVING THE SAME

A semiconductor wafer inspection system includes a wafer chuck disposed inside a chamber and on which a wafer is disposed, a light source configured to emit light for inspecting a pattern on the wafer to the wafer, an inspection controller configured to control the driving of the light source, a cooling gas gun disposed adjacent to the light source and configured to spray a cooling gas on a surface of the wafer, and a cooling controller configured to supply cooling air to the wafer chuck before light is emitted to the wafer and supply the cooling gas to the cooling gas gun.

WAFER STRESS CONTROL USING BACKSIDE FILM DEPOSITION AND LASER ANNEAL

In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.

METHOD AND DEVICE FOR PLACING SEMICONDUCTOR WAFER
20230061549 · 2023-03-02 ·

A method for processing a semiconductor wafer is provided. The method includes transferring the semiconductor wafer above a wafer placement device having a plate to align an edge of the semiconductor wafer with a first buffer member positioned in a peripheral region of the plate and to align a center of the semiconductor wafer with a second buffer member positioned in a central region of the plate. Each of the first buffer member and the second buffer member has a stiffness that is less than that of the plate. The method further includes lowering down the semiconductor wafer to place the semiconductor wafer over the plate.

SUBSTRATE ANALYSIS APPARATUS AND SUBSTRATE ANALYSIS METHOD

A substrate analysis apparatus is provided. The substrate analysis includes: an interlayer conveying module configured to transport a first FOUP; an exchange module which is connected to the interlayer conveying module, and configured to transfer a wafer from the first FOUP to a second FOUP; a pre-processing module configured to form a test wafer piece using the wafer inside the second FOUP; an analysis module configured to analyze the test wafer piece; and a transfer rail configured to transport the second FOUP containing the wafer and a tray containing the test wafer piece. The wafer includes a first identifier indicating information corresponding to the wafer, the test wafer piece includes a second identifier indicating information generated by the pre-processing module which corresponds to the test wafer piece, and the analysis module is configured to analyze the first identifier and the second identifier in connection with each other.

Enabling scanning electron microscope imaging while preventing sample damage on sensitive layers used in semiconductor manufacturing processes
11631602 · 2023-04-18 · ·

During electron beam imaging of a semiconductor wafer, the electron beam is adjusted to a first electron dose/nm.sup.2/time value below a damage threshold for an image frame grab of a site on the semiconductor wafer. Then the electron beam is adjusted to a second electron dose/nm.sup.2/time value different from the first electron dose/nm.sup.2/time value for a second image frame grab of the site. The second electron dose/nm.sup.2/time value can be above the damage threshold.