In an embodiment, a system includes: a tool port of a semiconductor processing tool; a processing port with an internal processing port location and an external processing port location; a robot configured to move a die vessel between the internal processing port location and the tool port; and an actuator configured to move the die vessel between the internal processing port location and the external processing port location.

Apparatus and methods for handling die carriers are disclosed. In one example, a disclosed apparatus includes: a load port configured to load a die carrier operable to hold a plurality of dies into a processing tool; and a lane changer coupled to the load port and configured to move at least one die in the die carrier to an input of the processing tool and transfer the at least one die into the processing tool for processing the at least one die.

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler. The control patterns may be part of a library of control patterns.

A wafer carrier assembly comprising a wafer carrier having a first and second side, the first side including: a circular recess configured to receive a semiconductor device wafer, and at least one cut-out arranged along the circumference of the circular recess. The first side also includes a carrier cover having a top and bottom side, the top side including: a plurality of gridlines extending to edges of the carrier cover, and a plurality of reticles extending from the top side to the bottom side where subsets of reticles are arranged to have a common center and each subset of reticles is arranged at each intersection of the plurality of gridlines.

A wafer carrier that exhibits a thin, low-profile includes a bottom support plate upon which a thinned semiconductor wafer may be positioned, with a holding ring disposed to surround the periphery of the wafer and engage with the bottom support plate to hold the wafer in a fixed position between the two components. The bottom support plate is formed to include a plurality of apertures for pulling a vacuum through the carrier, as well as features that engage with the holding ring and alignment fiducials for properly registering the orientation of the wafer's surface with respect to the wafer carrier and other testing equipment using the wafer carrier.

Disclosed herein are techniques for transferring particles in a pattern. In one implementation, a particle-transferring system includes a first substrate comprising a first surface configured to support a plurality of particles in a non-uniform pattern, and a particle transfer unit configured to remove the plurality of particles from the first surface in response to the plurality of particles being within a first gap. The system also includes a second substrate configured to remove the plurality of particles from the particle transfer unit and secure the plurality of particles to the second surface in response to the plurality of particles being within a second gap. The particle transfer unit is configured to transfer the plurality of particles and maintain the non-uniform pattern regardless of the positions of the plurality of particles, which are not predefined to fit features of the particle transfer unit.

A method for securing and verifying semiconductor wafers during fabrication includes receiving a semiconductor wafer after a layer of features has been patterned thereon. At least one security mark is formed at one or more locations embedded within a backside of the semiconductor wafer by implanting an inert species at the one or more locations. At a subsequent point in fabrication and/or after fabrication of the semiconductor wafer has completed the backside of the wafer is inspected for detection of the at least one security mark. If the at least one security mark is not detected at an expected location within the backside of the semiconductor wafer a determination is made that the semiconductor wafer has been compromised.

In certain embodiments, a system includes: a source lane configured to move a first die container between a load port and a source lane staging area; an inspection sensor configured to produce a sensor result based on a die on the first die container; a pass target lane configured to move a second die container between a pass target lane out port and a pass target lane staging area; a fail target lane configured to move a third die container between a fail target lane out port and a fail target lane staging area; and a conveyor configured to move the die from the first die container at the source lane staging area to either the second die container at the pass target lane staging area or the fail target lane staging area based on the sensor result.

In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes connecting a drum which stores the chemical liquid with a testing pipe. The method also includes guiding the chemical liquid in the drum into the testing pipe. In addition, the method includes detecting a condition of the chemical liquid in the testing pipe. The method further includes determining if the condition of the chemical liquid is acceptable. When the condition of the chemical liquid is acceptable, supplying the chemical liquid to a processing tool at which the semiconductor wafer is processed.

A semiconductor wafer transport apparatus having a transport arm and at least one end effector. An optical edge detection sensor is coupled to the transport arm and is configured so as to register and effect edge detection of a wafer supported by the end effector. An illumination source illuminates a surface of the wafer and is disposed with respect to the optical edge detection sensor so that the surface directs reflected surface illumination, from the illumination source, toward the optical edge detection sensor, and optically blanks, at the peripheral edge of the wafer, background reflection light of a background, viewed by the optical edge detection sensor coincident with linear traverse of the wafer supported by the at least one end effector. The peripheral edge of the wafer is defined in relief in image contrast to effect edge detection coincident with traverse of the wafer supported by the end effector.