A coating device for a tube-type PERC solar cell includes a wafer loading area, a furnace body, a gas cabinet, a vacuum system, a heating system, a control system and a graphite boat, wherein the gas cabinet is provided with a first gas line for feeding silane, a second gas line for feeding ammonia, a third gas line for feeding trimethylaluminum, a fourth gas line for feeding nitrous oxide, and a fifth gas line for feeding methane. The graphite boat is employed for loading and unloading a silicon wafer. Pre-processing is performed to the graphite boat before use or after several coating, wherein the pre-processing includes: baking the graphite boat and coating at least one layer of silicon carbide film on a surface of the baked graphite boat. The present application also discloses a coating method for a tube-type PERC solar cell.

A method for improving wafer bonding strength includes: Step S1: providing a silicon-based bonded wafer; Step S2: placing the bonded wafer in a microwave generating chamber; Step S3: raising the temperature in the microwave generating chamber and maintaining the temperature at a preset threshold by microwave heating; Step S4: after the bonded wafer reaches a predetermined temperature for a predetermined time period, shutting down the microwave power; and Step S5: cooling the bonded wafer. The present invention method can prevent waste of energy in the case of heating a small number of bonded wafers, and avoid a time-consuming preheating process. Therefore, the disclosed method is time-efficient and high-performance.

This specification describes semiconductor wafer carriers, methods for manufacturing the semiconductor wafer carriers, and methods for using the semiconductor wafer carriers. The semiconductor wafer carriers can include features for avoiding double-slotting, for preventing glove marks on semiconductor wafers, and for providing additional sitting and storage options for the wafer carrier. In some examples, a semiconductor wafer carrier includes multiple notched left-side rods that are parallel in a vertical direction and multiple notched right-side rods that are parallel in the vertical direction. The semiconductor wafer carrier includes one or more bottom rods. The left-side rods, the right-side rods, and the one or more bottom rods are joined to define semiconductor wafer slots.

A microLED mass transfer stamping system includes a stamp substrate with an array of trap sites, each configured with a columnar-shaped recess to temporarily secure a keel extended from a bottom surface of a microLED. In the case of surface mount microLEDs, the keel is electrically nonconductive. In the case of vertical microLEDs, the keel is an electrically conductive second electrode. The stamping system also includes a fluidic assembly carrier substrate with an array of wells having a pitch separating adjacent wells that matches the pitch separating the stamp substrate trap sites. A display substrate includes an array of microLED pads with the same pitch as the trap sites. The stamp substrate top surface is pressed against the display substrate, with each trap site interfacing a corresponding microLED site, and the microLEDs are transferred. Fluidic assembly stamp substrates are also presented for use with microLEDs having keels or axial leads.

An ESD protection composite structure includes a link layer, a progressive layer, and a composite layer. The link layer is used for disposing the ESD protection composite structure on a substrate, wherein a material of the link layer includes a metal material. The progressive layer is disposed on the link layer, wherein the material of the progressive layer includes a non-stoichiometric metal oxide material, and an oxygen concentration in the non-stoichiometric metal oxide material is increased gradually away from the substrate in a thickness direction of the progressive layer. The composite layer is disposed on the progressive layer, wherein the composite layer includes a stoichiometric metal oxide material and a non-stoichiometric metal oxide material, and a ratio of the non-stoichiometric metal oxide material and the stoichiometric metal oxide material in the composite layer may make a sheet resistance value of the composite layer 110.sup.7 /sq to 110.sup.8 /sq.

A microLED mass transfer stamping system includes a stamp substrate with an array of trap sites, each configured with a columnar-shaped recess to temporarily secure a keel extended from a bottom surface of a microLED. In the case of surface mount microLEDs, the keel is electrically nonconductive. In the case of vertical microLEDs, the keel is an electrically conductive second electrode. The stamping system also includes a fluidic assembly carrier substrate with an array of wells having a pitch separating adjacent wells that matches the pitch separating the stamp substrate trap sites. A display substrate includes an array of microLED pads with the same pitch as the trap sites. The stamp substrate top surface is pressed against the display substrate, with each trap site interfacing a corresponding microLED site, and the microLEDs are transferred. Fluidic assembly stamp substrates are also presented for use with microLEDs having keels or axial leads.

A microLED mass transfer stamping system includes a stamp substrate with an array of trap sites, each configured with a columnar-shaped recess to temporarily secure a keel extended from a bottom surface of a microLED. In the case of surface mount microLEDs, the keel is electrically nonconductive. In the case of vertical microLEDs, the keel is an electrically conductive second electrode. The stamping system also includes a fluidic assembly carrier substrate with an array of wells having a pitch separating adjacent wells that matches the pitch separating the stamp substrate trap sites. A display substrate includes an array of microLED pads with the same pitch as the trap sites. The stamp substrate top surface is pressed against the display substrate, with each trap site interfacing a corresponding microLED site, and the microLEDs are transferred. Fluidic assembly stamp substrates are also presented for use with microLEDs having keels or axial leads.

Provided is a transport fixing jig that has a high gripping force, hardly contaminates an object to be processed (object to be transported), and is excellent in heat resistance. The transport fixing jig of the present invention includes: a first base material; a carbon nanotube aggregate; and an adhesive layer arranged between the first base material and the carbon nanotube aggregate, wherein the first base material and the carbon nanotube aggregate are bonded to each other via the adhesive layer, and wherein a ratio (adhesive layer/base material) between a linear expansion coefficient of the first base material and a linear expansion coefficient of the adhesive layer is from 0.7 to 1.8.

This specification describes methods for processing semiconductor wafers, methods for loading semiconductor wafers into wafer carriers, and semiconductor wafer carriers. The methods and wafer carriers can be used for increasing the rigidity of wafers, e.g., large and thin wafers, by intentionally bowing the wafers to an extent that does not break the wafers. In some examples, a method for processing semiconductor wafers includes loading each semiconductor wafer into a respective semiconductor wafer slot of a semiconductor wafer carrier, horizontally bowing each semiconductor wafer, and moving the semiconductor wafer carrier into a processing station and processing the semiconductor wafers at the processing station while the semiconductor wafers are loaded into the semiconductor wafer carrier and horizontally bowed.

This specification describes semiconductor wafer carriers, methods for manufacturing the semiconductor wafer carriers, and methods for using the semiconductor wafer carriers. The semiconductor wafer carriers can include features for avoiding double-slotting, for preventing glove marks on semiconductor wafers, and for providing additional sitting and storage options for the wafer carrier. In some examples, a semiconductor wafer carrier includes multiple notched left-side rods that are parallel in a vertical direction and multiple notched right-side rods that are parallel in the vertical direction. The semiconductor wafer carrier includes one or more bottom rods. The left-side rods, the right-side rods, and the one or more bottom rods are joined to define semiconductor wafer slots.