A 3D semiconductor device including: a first level including a plurality of first metal layers; a second level, where the second level overlays the first level, where the second level includes at least one single crystal silicon layer, where the second level includes a plurality of transistors, where each transistor of the plurality of transistors includes a single crystal channel, where the second level includes a plurality of second metal layers, where the plurality of second metal layers include interconnections between the transistors of the plurality of transistors, and where the second level is overlaid by a first isolation layer; and a connective path between the plurality of transistors and the plurality of first metal layers, where the connective path includes a via disposed through at least the single crystal silicon layer, and where the via includes contact with at least one of the plurality of transistors.

An LDMOS includes a semiconductor substrate. A well is disposed within the semiconductor substrate. A body region is disposed within the well. A first gate electrode is disposed on the semiconductor substrate. A source electrode is disposed at one side of the first gate electrode. The source electrode includes a source contact area and numerous vias. The vias connect to the source contact area. The vias extend into the semiconductor substrate. A first drain electrode is disposed at another side of the first gate electrode and is opposed to the source electrode.

A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

A semiconductor device includes: a substrate; an ion-implanted silicon layer disposed in the substrate; a first insulator layer disposed over the ion-implanted silicon layer; an active device disposed over the first insulator layer; and a conductive via configured to penetrate the first insulator layer for coupling the ion-implanted silicon layer and the active device.

A metallization scheme for vertical field effect transistors (FETs) is provided. By forming lower-level local interconnects connecting source regions located at bottom portions of semiconductor fins, and upper-level interconnects connecting adjacent metal gates located along sidewalls of channel regions of the semiconductor fins, electrical connections to the source regions and the metal gates can be provided through the lower-level local interconnects and the upper-level local interconnects, respectively. As a result, gate, source and drain contact structures are formed on the same side of vertical FETs.

A fin field effect transistor device structure is provided. A fin field effect transistor device structure includes a first fin structure and a second fin structure on a substrate. The fin field effect transistor device structure also includes a spacer layer surrounding the first fin structure and the second fin structure. The fin field effect transistor device structure further includes a power rail over the spacer layer between the first fin structure and the second fin structure. In addition, the fin field effect transistor device structure includes a first contact structure covering the first fin structure and connected to the power rail.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming a first metal layer on top of first level; forming a second metal layer on top of the first metal layer; forming at least one second level above the second metal layer; performing a first lithography step on the second level; forming a third level on top of the second level; performing a second lithography step on the third level; perform processing steps to form first memory cells within the second level and second memory cells within the third level, where first memory cells include at least one second transistor, and the second memory cells include at least one third transistor; and deposit a gate electrode for the second and the third transistors simultaneously.

Embodiments disclosed herein include a semiconductor structure having a first lower device and a second lower device laterally adjacent to the first lower device at a lower level of the semiconductor structure, a first upper device and a second upper device laterally adjacent to the first upper device at an upper level of the semiconductor structure. The upper level may be vertically above the lower level. The semiconductor structure may also include an angled via electrically connecting the lower device and the first upper device. The angled via may include an angled surface laterally between the first upper device and the second upper device that is angled toward the first upper device relative to a vertical axis.

A semiconductor device includes a substrate, an active region, an isolation structure, a first metal line, gate structure, source/drain region, a source/drain contact, and a second metal line. The active region protrudes from a top surface of the substrate. The isolation structure is over the substrate and laterally surrounds the active region. The first metal line is in the isolation structure. The gate structure is over the active region. The source/drain region is in the active region. The source/drain contact is over the active region and is electrically connected to the source/drain region. The second metal line is over the gate structure and the source/drain contact, in which the second metal line vertically overlaps the first metal line.

A process for manufacturing an integrated circuit (IC) with a through via extending through a group III-V layer to a diode is provided. An etch is performed through the group III-V layer, into a semiconductor substrate underlying the group III-V layer, to form a via opening. A doped region is formed in the semiconductor substrate, through the via opening. Further, the doped region is formed with an opposite doping type as a surrounding region of the semiconductor substrate. The through via is formed in the via opening and in electrical communication with the doped region.