A controllable semiconductor component is produced by providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding from the top side into the semiconductor body and a second trench protruding from the top side into the semiconductor body. In a common process, an oxide layer is formed in the first trench and in the second trench such that the oxide layer fills the first trench and electrically insulates a surface of the second trench. The oxide layer is removed from the first trench completely or at least partly such that the semiconductor body has an exposed first surface area arranged in the first trench. An electrically conductive material is filled into the second trench, and the semiconductor body and the oxide layer are partially removed such that the electrically conductive material has an exposed second surface area at the bottom side.

A method for preparing a semiconductor device structure is provided. The method includes forming an isolation structure in a semiconductor substrate, and recessing the semiconductor substrate to form a first opening and a second opening. The first opening and the second opening are on opposite sides of the isolation structure, and a width of the second opening is greater than a width of the first opening. The method also includes forming an electrode layer over the semiconductor substrate. The first opening and the second opening are filled by the electrode layer. The method further includes polishing the electrode layer to form a gate electrode in the first opening and a resistor electrode in the second opening, and forming a source/drain (S/D) region in the semiconductor substrate. The S/D region is between the gate electrode and the isolation structure

In accordance with some embodiments, a semiconductor device is provided. The semiconductor device structure includes a substrate, and the substrate has a device region and an edge region. The semiconductor device structure also includes a silicon layer formed on the substrate and a transistor formed on the silicon layer. The transistor is formed at the device region of the substrate. The semiconductor device structure further includes a metal ring formed in the silicon layer. The metal ring is formed at the edge region of the substrate, and the transistor is surrounded by the metal ring.

A semiconductor device including at least one semiconductor device on a first surface of a dielectric layer, and at least one stressor structure having an intrinsic stress on a second surface of the dielectric layer. The at least one semiconductor device and the at least one stressor structure are present on opposing sides of the dielectric layer. The at least one stressor structure induces a stress on the at least one semiconductor device opposite the intrinsic stress.

An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

In one embodiment, a method of fabricating a semiconductor device having an isolated first transistor circuit and an isolated second transistor circuit is provided. The method comprises providing a silicon on insulator (SOI) wafer and fabricating an isolated first silicon region and an isolated second silicon region on the SOI wafer wherein each of the first silicon region and the second silicon region is bounded on its sides by a trench filled with insulator material. The method further comprises fabricating an active area comprising GaN on each of the first silicon region and the second silicon region to form the first transistor circuit and the second transistor circuit and fabricating source, drain, gate, and body connections for each of the first transistor circuit and the second transistor circuit.

A silicon on insulator substrate includes a semiconductor bulk handle wafer, an insulating layer on said semiconductor bulk handle wafer and a semiconductor film on said insulating layer. An opening extends completely through the semiconductor film and insulating layer to expose a surface of the semiconductor bulk handle wafer. Epitaxial material fills the opening and extends on said semiconductor film, with the epitaxial material and semiconductor film forming a thick semiconductor film. A trench isolation surrounds a region of the thick semiconductor film to define an electrical contact made to the semiconductor bulk handle wafer through the opening.

A solid-state image pickup unit including a pixel section having a plurality of unit pixels two-dimensionally arranged in a matrix formation, wherein a unit pixel includes a conductive region of a first conductivity type having a surface adjacent to a multilayer wiring layer, a charge accumulation region of a second conductivity type formed within the first conductive region, wherein the charge accumulation region is separated from the surface of the conductive region adjacent to the multilayer wiring layer by a separation section, and a contact disposed in the conductive region, the contact electrically connecting the charge accumulation region and an external wire of the multilayer wiring layer.

A method of forming a semiconductor structure in a semiconductor-on-insulator (SOI) substrate and semiconductor structure so formed are provided. The SOI substrate includes a semiconductor layer; a bulk semiconductor region underlying the semiconductor layer; and an insulation layer between the two. The structure includes first and second openings each having sidewalls, each of the first opening and the second opening formed substantially simultaneously and extending from a top surface of the semiconductor layer through the semiconductor layer and through the insulation layer to the conductive region; an insulating material adapted to provide electrical insulation to at least a portion of the side walls of the first opening; a semiconductor material at least partially filling the first opening, the semiconductor material defining an ohmic contact trench providing electrical contact with the semiconductor region; and an insulating material disposed in the second opening and defining a device isolation trench.

An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a first wire structure constructed to provide power to a portion of the first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and a second wire structure constructed to provide power to a portion of the second transistors, where the second wire structure is isolated from the first wire structure to provide a different power voltage to the portion of the second transistors.