An example IC structure includes a plurality of elongated channel structures (e.g., fins or nanoribbons) and one or more metal gate lines crossing over the fins/nanoribbons. A buried power rail (BPR) is formed between a pair of adjacent fins/nanoribbons. Once a BPR has been formed, an opening is formed above the BPR. The opening has an elongated shape that extends horizontally along the length of the BPR and extends vertically from the top of the BPR to the top of the IC structure, cutting through the metal gate lines. Portions of the opening between cut portions of metal gate lines may be filled with a dielectric material, thus forming metal gate cuts. A portion of the opening that is not between cut portions of a metal gate line is filled with an electrically conductive material and coupled to a source/drain contact of a transistor, thus forming a conductive via.

A semiconductor device according to the present disclosure includes a gate extension structure, a first source/drain feature and a second source/drain feature, a vertical stack of channel members extending between the first source/drain feature and the second source/drain feature along a direction, and a gate structure wrapping around each of the vertical stack of channel members. The gate extension structure is in direct contact with the first source/drain feature.

A metal insulator semiconductor field effect transistor (MISFET) such as a super junction metal oxide semiconductor FET with high voltage breakdown is realized by, in essence, stacking a relatively low aspect ratio column (trenches filled with dopant, e.g., p-type dopant) on top of a volume or volumes formed by implanting the dopant in lower layers. Together, the low aspect ratio column and the volume(s) form a continuous high aspect ratio column.

A method for manufacturing a semiconductor device includes providing a semiconductor substrate having a first side. A trench having a bottom is formed. The trench separates a first mesa region from a second mesa region formed in the semiconductor substrate. The trench is filled with an insulating material, and the second mesa region is removed relative to the insulating material filled in the trench to form a recess in the semiconductor substrate. In a common process, a first silicide layer is formed on and in contact with a top region of the first mesa region at the first side of the semiconductor substrate and a second silicide layer is formed on and in contact with the bottom of the recess.

The disclosed technology relates to methods for producing an interconnect structure on the back side of an integrated circuit chip. According to a first aspect, a via opening is etched in a top semiconductor layer, and filled with a sacrificial material, thereby forming a sacrificial pillar. Then front and back end of line portions are processed and the substrate is thinned. The etch stop layer and the sacrificial pillar are removed, and replaced an electrically conductive material forming a through semiconductor via. According to a second aspect, the sacrificial pillar is etched through the opening of a trench that intersects the pillar. Filling the trench with a conductive material also fills the cavity created by etching back the pillar resulting in an integral conductive pad and interconnect rail structure. The pillar can be removed and replaced by a conductive material, thereby creating the TSV connection.

A semiconductor structure includes a semiconductor substrate, a dielectric layer, a buffer layer, at least one recess, and at least one conductor. The dielectric layer is present on the semiconductor substrate. The buffer layer is present between the semiconductor substrate and the dielectric layer. The recess extends into the semiconductor substrate through the dielectric layer and the buffer layer, in which the buffer layer has a removing rate with respect to an etching process for forming the recess. The removing rate of the buffer layer is between those of the semiconductor substrate and the dielectric layer. The conductor is present in the recess.

Examples of an integrated circuit with an interconnect structure that includes a buried interconnect conductor and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a substrate that includes a plurality of fins extending from a remainder of the substrate. A spacer layer is formed between the plurality of fins, and a buried interconnect conductor is formed on the spacer layer between the plurality of fins. A set of capping layers is formed on the buried interconnect conductor between the plurality of fins. A contact recess is etched through the set of capping layers that exposes the buried interconnect conductor, and a contact is formed in the contact recess that is electrically coupled to the buried interconnect conductor.

Some embodiments of the disclosure provide a semiconductor device. The semiconductor device includes: a doped substrate; a barrier layer, disposed on the doped substrate; a channel layer, disposed between the doped substrate and the barrier layer; and a doped semiconductor structure, disposed in the doped substrate, where a band gap of the barrier layer is greater than a band gap of the channel layer, the doped substrate and the doped semiconductor structure have different polarities, and the doped substrate includes a doped silicon substrate.

A method of making an integrated circuit includes surrounding a first bias pad with dielectric material of a buried oxide layer. The method includes adding dopants to a layer of semiconductor material over the first bias pad. The method includes depositing a gate dielectric and a gate electrode over a top surface of the layer of semiconductor material. The method includes etching the gate dielectric and the gate electrode to isolate a gate electrode over the layer of semiconductor material. The method includes depositing an inter layer dielectric (ILD) material over the gate electrode and the layer of semiconductor material. The method includes etching at least one bias contact opening down to the first bias pad. The method includes filling the at least one bias contact opening with a bias contact material. The method includes electrically connecting at least one bias contact to an interconnect structure of the semiconductor device.

According to an aspect of the present inventive concept there is provided 3D IC, comprising: a plurality of logic cells stacked on top of each other, each logic cell forming part of one of a plurality of vertically stacked device tiers of the 3D IC, and each logic cell comprising a network of logic gates, each logic gate comprising a network of horizontal channel transistors, wherein a layout of the network of logic gates of each logic cell is identical among said logic cells such that each logic gate of any one of said logic cells has a corresponding logic gate in each other one of said logic cells, and wherein each logic cell comprises: a single active layer forming an active semiconductor pattern of the transistors of the logic gates of the logic cell, and a single layer of horizontally extending conductive lines comprising gate lines defining transistor gates of the transistors, and wiring lines forming interconnections in the network of transistors and in the network of logic gates of said logic cell.