A silicon carbide power device has: a die having a functional layer of silicon carbide and an edge area and an active area, surrounded by the edge area; gate structures formed on a top surface of the functional layer in the active area; and a gate contact pad for biasing the gate structures. The device also has an integrated resistor having a doped region, of a first conductivity type, arranged at the front surface of the functional layer in the edge area; wherein the integrated resistor defines an insulated resistance in the functional layer, interposed between the gate structures and the gate contact pad.

A silicon carbide power device has: a die having a functional layer of silicon carbide and an edge area and an active area, surrounded by the edge area; gate structures formed on a top surface of the functional layer in the active area; and a gate contact pad for biasing the gate structures. The device also has an integrated resistor having a doped region, of a first conductivity type, arranged at the front surface of the functional layer in the edge area; wherein the integrated resistor defines an insulated resistance in the functional layer, interposed between the gate structures and the gate contact pad.

The present technology relates to an imaging element that can increase the degree of freedom of element arrangement. A photoelectric conversion unit, a through trench penetrating a semiconductor substrate in a depth direction and formed between pixels each including the photoelectric conversion unit, and a PN junction region in a side wall of the trench are included, and the through trench has an opening portion, and a P-type region is formed in the opening portion. A photoelectric conversion unit, a holding unit, a through trench formed between the photoelectric conversion unit and the holding unit, and a PN junction region in a side wall of the through trench are included, and the through trench has an opening portion and a readout gate for reading the charge from the photoelectric conversion unit is formed in the opening portion. The present technology can be applied to, for example, an imaging element.

A split gate carrier stored trench bipolar transistor (CSTBT) with current clamping PMOS include a P-type buried layer and a split gate electrode with equal potential to an emitter metal on the basis of the traditional CSTBT, which effectively eliminates the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation effect, and helps to improve the trade-off relationship between the on-state voltage drop and the turn-off loss. Moreover, the introduction of a parasitic PMOS structure can reduce the saturation current and improve short-circuit safe operating area of the device, reduce the Miller capacitance, and improve the switching speed of the device and reduce the switching loss of the device. In addition, the split gate CSTBT integrating the split gate electrode and gate electrode in the same trench can shorten the distance between PMOS and NMOS channels.

A split gate carrier stored trench bipolar transistor (CSTBT) with current clamping PMOS include a P-type buried layer and a split gate electrode with equal potential to an emitter metal on the basis of the traditional CSTBT, which effectively eliminates the influence of an N-type carrier stored layer on breakdown characteristics of the device through the charge compensation effect, and helps to improve the trade-off relationship between the on-state voltage drop and the turn-off loss. Moreover, the introduction of a parasitic PMOS structure can reduce the saturation current and improve short-circuit safe operating area of the device, reduce the Miller capacitance, and improve the switching speed of the device and reduce the switching loss of the device. In addition, the split gate CSTBT integrating the split gate electrode and gate electrode in the same trench can shorten the distance between PMOS and NMOS channels.

A high-voltage isolation semiconductor device and a method for manufacturing the same. The method includes providing a first conductivity type substrate of a substrate layer; performing first conductivity type ion implantation by means of first implantation energy to form a first conductivity type buried layer part A; performing first conductivity type ion implantation by means of second implantation energy to form a first conductivity type buried layer part B primary structure, wherein the first implantation energy is greater than the second implantation energy; growing a second conductivity type epitaxial layer on the first conductivity type substrate, wherein the first conductivity type buried layer part B primary structure extends into the second conductivity type epitaxial layer to form a first conductivity type buried layer part B; and forming a first conductivity type well region by means of first conductivity type ion implantation.

Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

Provided is a landing pad structure including a substrate, a plurality of landing pads, a guard ring, and an edge pattern. The substrate includes a cell region, a periphery region, and a guard ring region located between the cell region and the periphery region. The landing pads are arranged on the substrate in the cell region in a hexagonal close packing (HCP) configuration. The guard ring is disposed on the substrate in the guard ring region in a strip form. The edge pattern is disposed on the substrate in the cell region and close to the guard ring region. A method of manufacturing the landing pad structure is also provided.

Transistor device and method of making thereof comprising a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type on top of the substrate. A body region doped with a second conductivity type is formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. An integrated planar-trench gate having a planar gate portion is formed on the surface of the epitaxial layer that is contiguous with a gate trench portion formed in the epitaxial layer.

Transistor device and method of making thereof comprising a substrate heavily doped with a first conductivity type and an epitaxial layer lightly doped with the first conductivity type on top of the substrate. A body region doped with a second conductivity type is formed in the epitaxial layer wherein the second conductivity type is opposite the first conductivity type and a source region doped with the first conductivity type is formed in the body region of the epitaxial layer. An integrated planar-trench gate having a planar gate portion is formed on the surface of the epitaxial layer that is contiguous with a gate trench portion formed in the epitaxial layer.