A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.

The disclosure provides a pattern collapse free wet clean process for fabricating semiconductor devices. By performing post reactive ion etching (RIE) using a fluorine-containing gas such as C.sub.2F.sub.6, followed by cleaning in a single wafer cleaner (SWC) with diluted hydrofluoric acid (HF) or in a solution of ammonia and HF, a substrate with multiple pattern collapse free high aspect ratio shallow trench isolation (STI) features can be obtained.

A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.

Disclosed is a semiconductor device including a first active pattern that extends in a first direction on an active region of a substrate, a first source/drain pattern in a recess on an upper portion of the first active pattern, a gate electrode that runs across a first channel pattern on the upper portion of the first active pattern and extends in a second direction intersecting the first direction, and an active contact electrically connected to the first source/drain pattern.

A method for making a semiconductor device may include forming shallow trench isolation (STI) regions in a semiconductor substrate defining an active region therebetween in the semiconductor substrate and a pad oxide on the active region. The method may further include removing at least some of the pad oxide, cleaning the active region to expose an upper surface thereof and define rounded shoulders of the active region adjacent the STI regions having an interior angle of at least 125°, and forming a superlattice on the active region. The superlattice may include a plurality of stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a semiconductor circuit including the superlattice.

Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

The invention relates to a silicon-based multifunction substrate. The silicon-based multifunction substrate comprises bulk silicon regions extending from a front surface to a back surface of the silicon-based multifunction substrate and at least one buried oxide layer laterally arranged between the bulk silicon regions. The buried oxide layer is covered by a structured silicon layer extending up to the front surface. The structured silicon layer comprises, laterally arranged between the bulk silicon regions, at least two silicon-on-insulator regions, herein SOI regions, with different thicknesses above the buried oxide layer. The SOI regions of the structured silicon layer are electrically insulated from each other by a respective first trench isolation extending from the front surface to the buried oxide layer.

The invention relates to a method for manufacturing a semiconductor-on-insulator structure (10), comprising the following steps: —providing an FD-SOI substrate (1) comprising, successively from its base to its top: a monocrystalline substrate (2) having an electrical resistivity of between 500 Ω.Math.cm and 30 kΩ.Math.cm, an interstitial oxygen content (Oi) of between 20 and 40 old ppma, and having an N- or P-type doping, an electrically insulating layer (3) having a thickness of between 20 nm and 400 nm, a monocrystalline layer (4) having a P-type doping, —heat-treating the FD-SOI substrate (1) at a temperature greater than or equal to 1175° C. for a time greater than or equal to 1 hour in order to form a P-N junction (5) in the substrate. The invention also relates to such a semiconductor-on-insulator structure.

A method of forming a semiconductor device includes forming a plurality of non-insulator structures on a substrate, the plurality of non-insulator structures being spaced apart by trenches, forming a sacrificial layer overfilling the trenches, reflowing the sacrificial layer at an elevated temperature, wherein a top surface of the sacrificial layer after the reflowing is lower than a top surface of the sacrificial layer before the reflowing, etching back the sacrificial layer to lower the top surface of the sacrificial layer to fall below top surfaces of the plurality of non-insulator structures, forming a dielectric layer on the sacrificial layer, and removing the sacrificial layer to form air gaps below the dielectric layer.