SUBSTRATE AND METHOD FOR MONOLITHIC INTEGRATION OF ELECTRONIC AND OPTOELECTRONIC DEVICES

Abstract

The invention relates to a silicon-based multifunction substrate. The silicon-based multifunction substrate comprises bulk silicon regions extending from a front surface to a back surface of the silicon-based multifunction substrate and at least one buried oxide layer laterally arranged between the bulk silicon regions. The buried oxide layer is covered by a structured silicon layer extending up to the front surface. The structured silicon layer comprises, laterally arranged between the bulk silicon regions, at least two silicon-on-insulator regions, herein SOI regions, with different thicknesses above the buried oxide layer. The SOI regions of the structured silicon layer are electrically insulated from each other by a respective first trench isolation extending from the front surface to the buried oxide layer.

Claims

1. A silicon-based multifunction substrate comprising: bulk silicon regions extending from a front surface to a back surface of the silicon multifunction substrate; at least one buried oxide layer laterally arranged between the bulk silicon regions; wherein the buried oxide layer is covered by a structured silicon layer extending up to the front surface to form a silicon-on-insulator, herein SOI, substrate region, the SOI substrate region comprising, later-ally arranged between the bulk silicon regions, at least two silicon-on-insulator regions with different thicknesses of the structured silicon layer above the buried oxide layer; wherein the SOI regions of the structured silicon layer are electrically insulated from each other by a respective first trench isolation extending from the front surface to the buried oxide layer; the structured silicon layer comprises only two types of SOI regions, namely at least one first SOI region and at least one second SOI region; the first SOI region has a first thickness and extends in thickness from the buried oxide layer to a first thickness level that is on an identical plane with the front surface of the bulk silicon region; and wherein the second SOI region has a second thickness larger than the first thickness and extends from the buried oxide layer to a second thickness level, which is on a plane different from that of the front surface of the bulk silicon region and thus forms a protrusion.

2. The silicon-based multifunction substrate according to claim 1, wherein the first SOI region of the structured silicon layer is laterally arranged between the second SOI region and the bulk silicon region.

3. The silicon-based multifunction substrate according to claim 2, wherein a lateral extension of the first SOI region is larger than 100 nanometer.

4. The silicon-based multifunction substrate according to claim 3, wherein the first SOI region and the bulk silicon region are electrically insulated from each other by a second trench isolation extending in a depth direction from the front surface to a depth level deeper than to a depth level that is deeper than an upper edge of the buried oxide layer.

5. The silicon-based multifunction substrate according to claim 4, wherein a lateral width on a bulk silicon side of the second trench isolation, is larger than the sum of a thickness of the buried oxide layer and the largest thickness of the structured silicon layer thicknesses.

6. An integrated circuit device, comprising: a silicon-based multifunction substrate for monolithic integration of electronic and optoelectronic devices according to claim 2, wherein active or passive electronic components are arranged on or within the bulk silicon regions forming a bulk electrical region, and wherein optical or opto-electronic components are arranged on top of or within the second SOI region of the structured silicon layer forming an optical SOI region.

7. The integrated circuit device according to claim 6, wherein further active electronic components are arranged on top of or within the first SOI region forming an electrical SOI region.

8. The integrated circuit device according to claim 7, wherein the further active electronic components comprise MOS components arranged on the electrical SOI region, which is laterally arranged between the optical SOI region and the bulk electrical region.

9. The integrated circuit device according to claim 8, wherein the active electronic components comprise active electronic radio-frequency components configured to receive electrical radio frequency signals or to provide electrical radio frequency signals.

10. A method fabricating a silicon-based multifunction substrate, the method comprising: providing silicon-on-insulator substrate that comprises a buried oxide layer and a silicon layer which is arranged on the buried oxide layer; forming at least one trench extending in a depth direction through the silicon layer and through the buried oxide layer; depositing silicon inside the trench to form a bulk silicon region that extends from a front surface to a back surface of the silicon multifunction substrate; and fabricating different silicon-on-insulator regions, herein SOI regions, with different thicknesses of the silicon layer above the buried oxide layer, including a first SOI region having a first thickness and a second SOI region having a second thickness larger than the first thickness and thus forms protrusions.

11. The method of claim 10, wherein fabricating the different SOI regions comprises thinning the silicon layer partially using a laterally structured mask.

12. The method of claim 10, wherein fabricating the different SOI regions comprises forming partially thickening the silicon layer using an epitaxial growth process and a laterally structured mask.

13. The method of claim 12, further comprising an oxidation of the front surface of the silicon-based multifunction substrate after fabricating the different SOI regions.

14. A method for fabricating an integrated circuit device, comprising fabricating silicon-based multifunction substrate according to the method of claim 10; fabricating transistors on at least one of the bulk silicon regions, thus forming bulk silicon electronic regions; fabricating at least one electronic component on of the at least one first SOI region; and fabricating at least one optical or opto-electronic component on the second SOI region.

15. The silicon-based multifunction substrate according to claim 1, wherein the first SOI region and the bulk silicon region are electrically insulated from each other by a second trench isolation extending in a depth direction from the front surface to a depth level deeper than to a depth level that is deeper than an upper edge of the buried oxide layer.

16. The silicon-based multifunction substrate according to claim 15, wherein a lateral width on a bulk silicon side of the second trench isolation, is larger than the sum of a thickness of the buried oxide layer and the largest thickness of the structured silicon layer thicknesses.

17. An integrated circuit device, comprising: a silicon-based multifunction substrate for monolithic integration of electronic and optoelectronic devices according to claim 1, wherein active or passive electronic components are arranged on or within the bulk silicon regions forming a bulk electrical region, and wherein optical or opto-electronic components are arranged on top of or within the second SOI region of the structured silicon layer forming an optical SOI region.

18. The integrated circuit device according to claim 6, wherein the active electronic components comprise active electronic radio-frequency components configured to receive electrical radio frequency signals or to provide electrical radio frequency signals.

19. The method of claim 10, further comprising an oxidation of the front surface of the silicon-based multifunction substrate after fabricating the different SOI regions.

Description

[0058] In the following, further embodiments will be described with reference to the enclosed drawings. In the drawings:

[0059] FIG. 1 shows a schematic cross-sectional view of a first embodiment of the silicon multifunction substrate;

[0060] FIG. 2 shows a schematic cross-sectional view of a second embodiment of the silicon multifunction substrate;

[0061] FIG. 3 shows a schematic cross-sectional view of an embodiment of the integrated circuit device;

[0062] FIG. 4 shows a block diagram of an embodiment of the method for fabricating a silicon multifunction substrate; and

[0063] FIG. 5 shows a block diagram of an embodiment of the method for fabricating an integrated circuit device.

[0064] FIG. 1 shows a schematic cross-sectional view of an embodiment of the silicon multifunction substrate 100 for monolithic integration of electronic and optoelectronic devices. The silicon multifunction substrate 100 comprises a bulk silicon region 102, which extends from a front surface 104 to a back surface 106 of the silicon multifunction substrate 100 and two buried oxide layers 108.1, 108.2 laterally arranged between the bulk silicon regions 102. The buried oxide layers 108.1, 108.2 are covered by structured silicon layers extending up to the front surface 104 of the silicon multifunction substrate 100 to form silicon-on-insulator substrate regions 110.1, 110.2. The silicon-on-insulator substrate regions 110.1, 110.2 comprise three silicon-on-insulator regions 112.1, 112.2, 114.1, 112.3, 112.4, 114.2 with two different thicknesses t2, t3 above the buried oxide layers 108.1, 108.2. In this embodiment, the silicon-on-insulator regions 112.1, 112.2, 112.3, 112.4 have the thickness t2 and the silicon-on-insulator regions114.1, 114.2 has the thickness t3. The buried oxide layers 108.1, 108.2 have in lateral extension a constant thickness t1. In this embodiment, the thickness t3 of second silicon-on-insulator regions 114.1, 114.2, which is arranged adjacent laterally to first silicon-on-insulator regions 112.1, 112.4, 112.2, 112.3, is larger than the thickness t2 of the first silicon-on-insulator regions 112.1, 112.2, 112.3, 112.4. Thus, the thickness t3 of the second silicon-on-insulator regions 114.1, 114.2 protrudes on a plane different from that of the front surface 104 of the bulk silicon region 102.

[0065] In this embodiment of the multifunction substrate the thickness t2 is 140 nanometer, the thickness t3 is 220 nanometer and the thickness t1 is 2 micrometer.

[0066] Neighboring lateral SOI regions 112.1, 112.2, 114.1, 112.3, 112.4, 114.2 of the silicon-on-insulator substrate regions 110.1, 110.2 are electrically insulated from each other by a respective first trench isolation 116.1, 116.2, 116.3, 116.4. The first trench isolation 116.1, 116.2, 116.3, 116.4 extends from the front surface 104 to the buried oxide layer 108.1, 108.2.

[0067] The first silicon-on-isolator regions 112.1, 112.2, 112.3, 112.4 are laterally arranged between the second lateral SOI region 114.1, 114.2 and the bulk silicon region 102. Thus, a low-loss interconnects are formed. The bulk silicon region 102 and the first silicon-on-isolator regions 112.1, 112.2, 112.3, 112.4 are electrically insulated from each other by a second trench isolation 118.1, 118.2. The second isolation trench has a thickness t.sub.ST, which extends in a depth direction D from the front surface 104 to a depth level deeper than an upper edge of the buried oxide layer 108.1, 108.2. In this embodiment, the thickness t.sub.ST is 400 nanometer.

[0068] In other embodiments, the thickness t.sub.ST is between 250 nanometer and 500 nanometer.

[0069] A lateral width W1 of the first lateral SOI regions 112.1, 112.2, 112.3, 112.4 is larger than 100 nanometer.

[0070] The lateral width W.sub.ST of the second trench isolation 118.1, 118.2, 118.3, 118.4 is the sum of a lateral width of the second trench isolation on the bulk silicon side W.sub.STb and of a lateral width of the second trench isolation on the SOI side W.sub.STs. The lateral width of the second trench isolation on the bulk silicon side W.sub.STb is a lateral extension of the second trench isolation in the bulk silicon region. The width W.sub.STb is larger than the sum of the thickness t1 of the buried oxide layer 108.1, 108.2 and the thickness t3 of the second silicon-on-insulator regions 114.1, 114.2.The lateral width W.sub.STb of the second trench isolation118.1, 118.2, 118.3, 118.4 is suitable to reduce negative effects that can be caused by defects induced during the fabrication of the multifunction substrate. Such defects can be crystallinity defects in the bulk silicon region 102.

[0071] FIG. 2 shows a schematic cross-sectional view of a second embodiment of a silicon multifunction substrate 100′. The following discussion will focus on differences between the silicon multifunction substrate 100 of FIG. 1 and the silicon multifunction substrate 100′ of FIG. 2. Those features that are not altered are referred to using the same reference numerals as used in FIG. 1.

[0072] The silicon multifunctional substrate 100′ has undercuts 120.1, 120.2, 120.3, 120.4 induced by wet etching during the fabrication of the bulk silicon region. A lateral width W.sub.ST of the second trench isolation 118.1, 118.2, 118.3, 118.4 is the sum of a lateral width of the second trench isolation on the bulk silicon side W.sub.STb and a lateral width of the second trench isolation on the SOI side W.sub.STs. Here, the lateral width of the second isolation trench on the SOI side W.sub.STs is larger than the thickness of the buried oxide layer 108.1, 108.2. Such a lateral width of the second trench isolation on the SOI side W.sub.STs is suitable to prevent negative effects on electronic components.

[0073] FIG. 3 shows a schematic cross-sectional view of an embodiment of the integrated circuit device 200. The integrated circuit device 200 includes the silicon multifunction substrate 100 of FIG. 1. Thus, the numbering of those components of FIG. 3, which have a correspondence in the embodiment of FIG. 1, can be converted to the numbering of FIG. 1 by subtracting 100 from each number. Therefore, reference is also made to the description of FIG. 1.

[0074] The integrated circuit device 200 of FIG. 3 comprises in addition to the silicon multifunction substrate 100 of FIG. 1, an RF bipolar transistor 202 with base and emitter structures on top of and a collector structure largely within the bulk silicon region 102, photodiodes 204.1, 204.2, which are arranged on top of or partly within the second lateral SOI regions 114.1, 114.2, and CMOS transistors 206.1, 206.2 with gate structures which are arranged on top of the first lateral SOI regions 112.1, 112.3.

[0075] The RF bipolar transistor 202 with structures on top of and within the bulk silicon region 102 forms a bulk electrical region. The photodiodes 204.1, 204.2, arranged on top of or partly within the second lateral SOI regions 114.1, 114.2 form optical SOI regions and the MOS transistors 206.1, 206.2 with gate structures arranged on top of the first lateral SOI regions 112.1, 112.3 form electrical SOI regions. The placement of such different regions is starting with a bulk electrical region and ending with another bulk electrical region: bulk electrical region—electrical SOI region—optical SOI region—electrical SOI region—bulk electrical region.

[0076] The optical and electronic components are not limiting to such examples. In other variants of the integrated circuit device 200 of FIG. 3 numerous bipolar transistors or CMOS transistors can be arranged on top of the bulk silicon region. Further, optical components can be waveguides or light modulators and electronic components can be passive electronic components like resistors. In such alternatives the thicknesses t1, t2 and t3 of the silicon multifunction substrate 100 are selected with respect of the respective requirements of the respective components.

[0077] The RF bipolar transistor 202, the photodiodes 204.1, 204.2 and the MOS transistors or resistors 206.1, 206.2 can be fabricated by FEOL technology and electrically connected via electric interconnects 208.

[0078] FIG. 4 shows a block diagram of an embodiment of the method 300 for fabricating a silicon multifunction substrate 100 for monolithic integration of electronic and optoelectronic devices, which is explained in FIG. 1.

[0079] The method for fabricating a silicon multifunction substrate starts from an industry-standard silicon-on-insulator (SOI) substrate that comprises a buried oxide layer and a silicon layer which is arranged on the buried oxide layer. A first step 302 of the method is providing a silicon-on-insulator substrate that comprises a buried oxide layer and a silicon layer which is arranged on the buried oxide layer. A bulk silicon substrate region is fabricated in a second step 304 by forming a trench that extends in a depth direction through the silicon layer and through the buried oxide layer and depositing in step 306 silicon inside the trench. The silicon inside the trench is epitaxially grown. In a next fabrication step 308, different lateral silicon-on-insulator regions with different thicknesses of the silicon layer above the buried oxide layer are fabricated. The step 308 fabricating the different SOI regions comprises thinning the silicon layer partially using a laterally structured mask, which protects the optical SOI regions. The silicon layer is thinned by a sequence of reactive ion etching (RIE) and wet etching steps. Alternatively, thinning can be done by thermal oxidation and subsequent removing, preferably by a wet etching step, the formed silicon oxide layer.

[0080] As alternative to step 308, fabricating the different SOI regions comprises partially thickening the silicon layer using a laterally structured mask, which protects here the electrical SOI regions.

[0081] The different thicknesses of the structured silicon layer above the buried oxide layer form protrusions for some of the different thicknesses. In a further fabrication step 310, an oxidation of the front surface of the silicon multifunction substrate after fabricating the different lateral SOI regions is carried out.

[0082] FIG. 5 shows a block diagram of an embodiment of the method 400 for fabricating an integrated circuit device 200 of FIG. 3. A first step 402 of this method is fabricating a silicon multifunction substrate with the method explained in context of FIG. 4. In a second step 404, bipolar transistors are fabricated on top of the bulk silicon region. Thus, a bulk silicon electronic region is formed. In a third step 406, electronic components are fabricated on top of the first SOI region forming an electrical SOI region. In a last step 408, optical or opto-electronic components are fabricated on top of the second SOI region forming an optical SOI region.

[0083] In summary, the invention relates to a silicon-based multifunction substrate. The multifunction substrate comprises bulk silicon regions extending from a front surface to a back surface of the silicon-based multifunction substrate and at least one buried oxide layer laterally arranged between the bulk silicon regions. The buried oxide layer is covered by a structured silicon layer extending up to the front surface. The structured silicon layer comprises, laterally arranged between the bulk silicon regions, at least two silicon-on-insulator regions, herein SOI regions, with different thicknesses above the buried oxide layer. The SOI regions of the structured silicon layer are electrically insulated from each other by a respective first trench isolation extending from the front surface to the buried oxide layer.