Disclosed is a bulk semiconductor structure that includes a semiconductor substrate with a multi-level polycrystalline semiconductor region that includes one or more first-level portions (i.e., buried portions) and one or more second-level portions (i.e., non-buried portions). Each first-level portion can be within the semiconductor substrate some distance below the top surface (i.e., buried), can be aligned below a monocrystalline semiconductor region and/or a trench isolation region, and can have a first maximum depth. Each second-level portion can be within the semiconductor substrate at the top surface, can be positioned laterally adjacent to a trench isolation region, and can have a second maximum depth that is less than the first maximum depth. Also disclosed herein are method embodiments for forming the bulk semiconductor structure wherein the first-level and second-level portions of the multi-level polycrystalline semiconductor region are concurrently formed (e.g., using a single module).

Disclosed is a bulk semiconductor structure that includes a semiconductor substrate with a multi-level polycrystalline semiconductor region that includes one or more first-level portions (i.e., buried portions) and one or more second-level portions (i.e., non-buried portions). Each first-level portion can be within the semiconductor substrate some distance below the top surface (i.e., buried), can be aligned below a monocrystalline semiconductor region and/or a trench isolation region, and can have a first maximum depth. Each second-level portion can be within the semiconductor substrate at the top surface, can be positioned laterally adjacent to a trench isolation region, and can have a second maximum depth that is less than the first maximum depth. Also disclosed herein are method embodiments for forming the bulk semiconductor structure wherein the first-level and second-level portions of the multi-level polycrystalline semiconductor region are concurrently formed (e.g., using a single module).

A method of manufacturing a semiconductor device includes forming a plurality of fins by forming a plurality of first device isolating trenches repeated at a first pitch in a substrate, forming a plurality of fin-type active areas protruding from a top surface of a first device isolating layer by forming the first device isolating layer in the plurality of first device isolating trenches, forming a plurality of second device isolating trenches at a pitch different from the first pitch by etching a portion of the substrate and the first device isolating layer, and forming a second device isolating layer in the plurality of second device isolating trenches, so as to form a plurality of fin-type active area groups separated from each other with the second device isolating layer therebetween.

A semiconductor device includes a polycrystalline silicon part buried in a termination region of a silicon layer. The polycrystalline silicon part contacts the silicon layer, has a higher crystal grain density than the silicon layer, and includes a heavy metal. The silicon layer includes a drift layer located in a cell region and the termination region. The drift layer has a lower first-conductivity-type impurity concentration than a silicon substrate. The drift layer includes a same element of heavy metal as the heavy metal included in the polycrystalline silicon part.

A semiconductor device includes a polycrystalline silicon part buried in a termination region of a silicon layer. The polycrystalline silicon part contacts the silicon layer, has a higher crystal grain density than the silicon layer, and includes a heavy metal. The silicon layer includes a drift layer located in a cell region and the termination region. The drift layer has a lower first-conductivity-type impurity concentration than a silicon substrate. The drift layer includes a same element of heavy metal as the heavy metal included in the polycrystalline silicon part.

A semiconductor device, and methods of forming the same. In one example, the semiconductor device includes a trench in a substrate having a top surface, and a shield within the trench. The semiconductor device also includes a shield liner between a sidewall of the trench and the shield, and a lateral insulator over the shield contacting the shield liner. The semiconductor device also includes a gate dielectric layer on an exposed sidewall of the trench between the lateral insulator and the top surface. The lateral insulator may have a minimum thickness at least two times thicker than a maximum thickness of the gate dielectric layer.

A structure includes a semiconductor-on-insulator (SOI) substrate including a semiconductor substrate, a buried insulator layer over the semiconductor substrate, and an SOI layer over the buried insulator layer. At least one polycrystalline active region fill shape is in the SOI layer. A polycrystalline isolation region may be in the semiconductor substrate under the buried insulator layer. The at least one polycrystalline active region fill shape is laterally aligned over the polycrystalline isolation region, where provided. Where provided, the polycrystalline isolation region may extend to different depths in the semiconductor substrate.

A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode that is formed on the first source region, a second drain region that is connected to the first source region, a second source region that is formed separated from the second drain region, a first floating electrode that is connected to the second source region and to the channel region, first gate electrodes, and a second gate electrode that is connected to the first gate electrodes.

A power semiconductor device includes a semiconductor body having a drift region of a first conductivity type inside an active region. An edge termination region includes: a guard region of a second conductivity type at a front side of the semiconductor body and surrounding the active region; and a field plate trench structure extending vertically into the body from the front side and at least partially filled with a conductive material that is electrically connected with the guard region and insulated from the body external of the guard region. A first portion of the field plate trench structure at least partially extends into the guard region and is at least partially arranged below a metal layer arranged at the front side. A second portion of the field plate trench structure extends outside of the guard region and surrounds the active area, the metal layer not extending above the second portion.

In accordance with embodiments of the present disclosure, an integrated circuit may include at least one region of shallow-trench isolation field oxide, at least one region of dummy diffusion, and a polycrystalline semiconductor resistor. The at least one region of shallow-trench isolation field oxide may be formed on a semiconductor substrate. The at least one region of dummy diffusion may be formed adjacent to the at least one region of shallow-trench isolation field oxide on the semiconductor substrate. The polycrystalline semiconductor resistor may comprise at least one resistor arm formed with a polycrystalline semiconductor material, wherein the at least one resistor arm is formed over each of the at least one region of shallow-trench isolation field oxide and the at least one region of dummy diffusion.