A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

A method for manufacturing a device may include providing an ultra-high voltage (UHV) component that includes a source region and a drain region, and forming an oxide layer on a top surface of the UHV component. The method may include connecting a low voltage terminal to the source region of the UHV component, and connecting a high voltage terminal to the drain region of the UHV component. The method may include forming a shielding structure on a surface of the oxide layer provided above the drain region of the UHV component, forming a high voltage interconnection that connects to the shielding structure and to the high voltage terminal, and forming a metal routing that connects the shielding structure and the low voltage terminal.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

A method and a transistor device are disclosed. The method includes: forming a trench in a first surface in an edge region of a semiconductor body; forming an insulation layer in the trench and on the first surface of the semiconductor body; and planarizing the insulation layer so that a trench insulation layer that fills the trench remains, wherein forming the insulation layer comprises a thermal oxidation process.

A method and a transistor device are disclosed. The method includes: forming a trench in a first surface in an edge region of a semiconductor body; forming an insulation layer in the trench and on the first surface of the semiconductor body; and planarizing the insulation layer so that a trench insulation layer that fills the trench remains, wherein forming the insulation layer comprises a thermal oxidation process.

The present invention provides a power device with super junction structure (or referred to as super junction power device) in both cell region and edge termination region and a method of making the same. A floating island of a second conductivity type of a cell region, a floating island of the second conductivity type of a termination region, a pillar of the second conductivity type of the cell region and a pillar of the second conductivity type of the termination region may be formed through adding a super junction mask (or reticle) after forming the epitaxial layer of a first conductivity type, through a well mask (or reticle) before or after forming a well of the second conductivity type, and through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high. A breakdown voltage may be raised and both Miller capacitance and input capacitance can be decreased, an on-state resistance can be decreased because of the floating island of the second conductivity type and the pillar of the second conductivity type of the cell region. A withstand (block) voltage in the termination region may be raised, an area thereof may be reduced, and a whole area of a high voltage device may be decreased because of the floating island of the second conductivity type and the pillar of the second conductivity type of the termination region.

The present invention provides a power device with super junction structure (or referred to as super junction power device) in both cell region and edge termination region and a method of making the same. A floating island of a second conductivity type of a cell region, a floating island of the second conductivity type of a termination region, a pillar of the second conductivity type of the cell region and a pillar of the second conductivity type of the termination region may be formed through adding a super junction mask (or reticle) after forming the epitaxial layer of a first conductivity type, through a well mask (or reticle) before or after forming a well of the second conductivity type, and through a contact mask (or reticle) before or after forming a contact structure. Multiple epitaxial processes and deep trench etching process may not be needed. Therefore, the process is simple, the cost is low and yield and reliability are high. A breakdown voltage may be raised and both Miller capacitance and input capacitance can be decreased, an on-state resistance can be decreased because of the floating island of the second conductivity type and the pillar of the second conductivity type of the cell region. A withstand (block) voltage in the termination region may be raised, an area thereof may be reduced, and a whole area of a high voltage device may be decreased because of the floating island of the second conductivity type and the pillar of the second conductivity type of the termination region.

According to one embodiment, a semiconductor device includes a semiconductor member, first and second electrodes, a gate electrode, a gate terminal, a first conductive member, a first terminal, and a first insulating member. The semiconductor member includes first and second semiconductor regions, and a third semiconductor region provided between the first and second semiconductor regions. The first electrode is electrically connected to the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The gate terminal is electrically connected to the gate electrode. The first conductive member is electrically insulated from the first and second electrodes, and the gate electrode. The first terminal is electrically connected to the first conductive member. The first insulating member includes a first insulating region between the third semiconductor region and the gate electrode, and a second insulating region between the gate electrode and the first conductive member.

According to one embodiment, a semiconductor device includes a semiconductor member, first and second electrodes, a gate electrode, a gate terminal, a first conductive member, a first terminal, and a first insulating member. The semiconductor member includes first and second semiconductor regions, and a third semiconductor region provided between the first and second semiconductor regions. The first electrode is electrically connected to the first semiconductor region. The second electrode is electrically connected to the second semiconductor region. The gate terminal is electrically connected to the gate electrode. The first conductive member is electrically insulated from the first and second electrodes, and the gate electrode. The first terminal is electrically connected to the first conductive member. The first insulating member includes a first insulating region between the third semiconductor region and the gate electrode, and a second insulating region between the gate electrode and the first conductive member.