A method includes providing a semiconductor substrate, and forming a first N-type implant region and a second N-type implant region in the semiconductor substrate. The first N-type implant region and the second N-type implant region are separated by a portion of the semiconductor substrate. The method also includes forming a first P-type implant region in the semiconductor substrate, and performing a heat treatment process on the semiconductor substrate to form an N-type well region and a P-type well region in the semiconductor substrate. The N-type well region has a first portion, a second portion, and a third portion between the first portion and the second portion. The doping concentration of the third portion is lower than the doping concentration of the first portion and the doping concentration of the second portion.

A method includes providing a semiconductor substrate, and forming a first N-type implant region and a second N-type implant region in the semiconductor substrate. The first N-type implant region and the second N-type implant region are separated by a portion of the semiconductor substrate. The method also includes forming a first P-type implant region in the semiconductor substrate, and performing a heat treatment process on the semiconductor substrate to form an N-type well region and a P-type well region in the semiconductor substrate. The N-type well region has a first portion, a second portion, and a third portion between the first portion and the second portion. The doping concentration of the third portion is lower than the doping concentration of the first portion and the doping concentration of the second portion.

A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Log.sub.e (L.sup.2/SD), the dispersion degree is not less than 2 and not more than 15.

A semiconductor device includes a semiconductor layer that has a first main surface at one side and a second main surface at another side and includes an active region, a plurality of IGBT regions that are formed in the active region, and a plurality of diode regions that are formed in the active region such as to be adjacent to the plurality of IGBT regions, and where when a total extension of boundary lines between the plurality of IGBT regions and the plurality of diode regions is represented by L, a total area of the plurality of diode regions is represented by SD, and a dispersion degree of the plurality of diode regions with respect to the active region is defined by a formula Log.sub.e (L.sup.2/SD), the dispersion degree is not less than 2 and not more than 15.

Embodiments of this application disclose a semiconductor device and a manufacturing method thereof The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate and having a first bandgap, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a second bandgap. The second bandgap is larger than the first bandgap. The semiconductor device further includes a gate contact disposed over the second nitride semiconductor layer and a first field plate disposed over the gate contact. The first field plate has a first surface facing the substrate, a second surface facing the substrate, and a protruded portion. The protruded portion has a bottom surface facing the substrate. The bottom surface is located between the first surface and the second surface.

Embodiments of this application disclose a semiconductor device and a manufacturing method thereof The semiconductor device includes a substrate, a first nitride semiconductor layer disposed on the substrate and having a first bandgap, and a second nitride semiconductor layer disposed on the first nitride semiconductor layer and having a second bandgap. The second bandgap is larger than the first bandgap. The semiconductor device further includes a gate contact disposed over the second nitride semiconductor layer and a first field plate disposed over the gate contact. The first field plate has a first surface facing the substrate, a second surface facing the substrate, and a protruded portion. The protruded portion has a bottom surface facing the substrate. The bottom surface is located between the first surface and the second surface.

A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.

A high-threshold-voltage normally-off high-electron-mobility transistor (HEMT) includes a nucleation layer and an epitaxial layer are grown sequentially on a substrate; a barrier layer, a source, and a drain above the epitaxial layer; the barrier layer and the epitaxial layer form a heterojunction structure, and the contact interface therebetween is induced by polarization charges to generate two-dimensional electron gas. The HEMT includes a passivation layer above the barrier layer; a gate cap layer above the gate region barrier layer; the upper part of the gate cap layer is subjected to surface plasma oxidation to form an oxide dielectric layer, or a single-layer or multiple gate dielectric insertion layer is directly deposited thereon. The HEMT includes a gate is located above the gate dielectric insertion layer; the gate is in contact with the passivation layer; and a field plate extends from the gate to the drain on the passivation layer.

A high-threshold-voltage normally-off high-electron-mobility transistor (HEMT) includes a nucleation layer and an epitaxial layer are grown sequentially on a substrate; a barrier layer, a source, and a drain above the epitaxial layer; the barrier layer and the epitaxial layer form a heterojunction structure, and the contact interface therebetween is induced by polarization charges to generate two-dimensional electron gas. The HEMT includes a passivation layer above the barrier layer; a gate cap layer above the gate region barrier layer; the upper part of the gate cap layer is subjected to surface plasma oxidation to form an oxide dielectric layer, or a single-layer or multiple gate dielectric insertion layer is directly deposited thereon. The HEMT includes a gate is located above the gate dielectric insertion layer; the gate is in contact with the passivation layer; and a field plate extends from the gate to the drain on the passivation layer.

A process is proposed for manufacturing an integrated device having at least one MOS transistor integrated on a die of semiconductor material. The process includes forming one or more gate trenches with corresponding field plates and gate regions. A body region is formed by implanting dopants selectively along one or more implantation directions that are tilted with respect to a front surface of the die. Moreover, a corresponding integrated device and a system comprising this integrated device are proposed.