A semiconductor device is provided, which includes a substrate, a first and second doped wells, a drain and source regions, a gate structure, a field plate and a booster plate. The first and second doped wells are arranged in the substrate. The drain region is arranged in the first doped well and the source region is arranged in the second doped well. The gate structure is arranged over the substrate and between the source and drain regions. The field plate is arranged over the first doped well and the booster plate arranged between the field plate and the first doped well.

A semiconductor device includes a core gate and a pair of isolation gates. The core gate has a first stack of two or more layers, the first stack including at least (i) a first dielectric layer having a first thickness and (ii) a first electrode layer. The isolation gates are formed on first and second sides of the core gate. The isolation gates are configured to electrically isolate the core gate. At least one of the isolation gates has a second stack of two or more layers, the second stack including at least (i) a second dielectric layer having a second thickness greater than the first thickness and (ii) a second electrode layer.

A semiconductor device includes a core gate and a pair of isolation gates. The core gate has a first stack of two or more layers, the first stack including at least (i) a first dielectric layer having a first thickness and (ii) a first electrode layer. The isolation gates are formed on first and second sides of the core gate. The isolation gates are configured to electrically isolate the core gate. At least one of the isolation gates has a second stack of two or more layers, the second stack including at least (i) a second dielectric layer having a second thickness greater than the first thickness and (ii) a second electrode layer.

The disclosure relates to a semiconductor die with a transistor device, having a source region, a drain region, a body region including a channel region, a gate region, which includes a gate electrode, next to the channel region, for controlling a channel formation, a drift region between the channel region and the drain region, and a field electrode region with a field electrode formed in a field electrode trench, which extends into the drift region, wherein the channel region extends laterally and is aligned vertically with the gate region, and wherein at least a portion of the channel region is arranged vertically above the field electrode region.

The disclosure relates to a semiconductor die with a transistor device, having a source region, a drain region, a body region including a channel region, a gate region, which includes a gate electrode, next to the channel region, for controlling a channel formation, a drift region between the channel region and the drain region, and a field electrode region with a field electrode formed in a field electrode trench, which extends into the drift region, wherein the channel region extends laterally and is aligned vertically with the gate region, and wherein at least a portion of the channel region is arranged vertically above the field electrode region.

An embodiment of a semiconductor device includes a semiconductor substrate, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor, a control electrode formed over the semiconductor substrate between the first current carrying electrode and the second current carrying electrode, and a first dielectric layer disposed over the control electrode, and a second dielectric layer disposed over the first dielectric layer. A first opening is formed in the second dielectric layer, adjacent the control electrode and the second current-carrying electrode, having a first edge laterally adjacent to and nearer the second current-carrying electrode, and a second edge laterally adjacent to and nearer to the control electrode, and a conductive element formed over the first dielectric layer and within the first opening, wherein the portion of the conductive element formed within the first opening forms a first metal-insulator-semiconductor region within the first opening.

An embodiment of a semiconductor device includes a semiconductor substrate, a first current-carrying electrode, and a second current-carrying electrode formed over the semiconductor, a control electrode formed over the semiconductor substrate between the first current carrying electrode and the second current carrying electrode, and a first dielectric layer disposed over the control electrode, and a second dielectric layer disposed over the first dielectric layer. A first opening is formed in the second dielectric layer, adjacent the control electrode and the second current-carrying electrode, having a first edge laterally adjacent to and nearer the second current-carrying electrode, and a second edge laterally adjacent to and nearer to the control electrode, and a conductive element formed over the first dielectric layer and within the first opening, wherein the portion of the conductive element formed within the first opening forms a first metal-insulator-semiconductor region within the first opening.

A GaN-based high electron mobility transistor (HEMT) device includes a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate, a drain contact and a source contact on the barrier layer, and a gate contact on the barrier layer between the drain contact and the source contact. A sheet resistance of a drain access region and/or a source access region of the semiconductor structure is between 300 and 400 Ω/sq.

A GaN-based high electron mobility transistor (HEMT) device includes a semiconductor structure comprising a channel layer and a barrier layer sequentially stacked on a substrate, a drain contact and a source contact on the barrier layer, and a gate contact on the barrier layer between the drain contact and the source contact. A sheet resistance of a drain access region and/or a source access region of the semiconductor structure is between 300 and 400 Ω/sq.

A transistor device according to some embodiments includes a channel layer, a barrier layer on the channel layer, and source and drain contacts on the barrier layer, and a gate contact on the barrier layer between the source and drain contacts. The channel layer includes a sub-layer having an increased doping concentration level relative to a remaining portion of the channel layer. The presence of the sub-layer may reduce drain lag without substantially increasing gate lag.