SEMICONDUCTOR DIE WITH A TRANSISTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Abstract

The disclosure relates to a semiconductor die with a transistor device, having a source region, a drain region, a body region including a channel region, a gate region, which includes a gate electrode, next to the channel region, for controlling a channel formation, a drift region between the channel region and the drain region, and a field electrode region with a field electrode formed in a field electrode trench, which extends into the drift region, wherein the channel region extends laterally and is aligned vertically with the gate region, and wherein at least a portion of the channel region is arranged vertically above the field electrode region.

Claims

1. A semiconductor die with a transistor device, comprising: a source region: a drain region; a body region comprising a channel region; a gate region which comprises a gate electrode next to the channel region, for controlling a channel formation; a drift region between the channel region and the drain region; and a field electrode region with a field electrode formed in a field electrode trench which extends into the drift region; wherein the channel region extends laterally and is aligned vertically with the gate region, wherein at least a portion of the channel region is arranged vertically above the field electrode region.

2. The semiconductor die of claim 1, wherein the source region is arranged vertically above the field electrode region.

3. The semiconductor die of claim 1, further comprising a source contact which extends vertically into the source region and is arranged vertically above the field electrode.

4. The semiconductor die of claim 3, further comprising an insulating spacer formed vertically above the field electrode in the field electrode trench, wherein the source contact extends to the insulating spacer.

5. The semiconductor die of claim 1, further comprising an insulating spacer formed vertically above the field electrode in the field electrode trench, wherein an upper end of the insulating spacer is recessed into the field electrode trench.

6. The semiconductor die of claim 1, further comprising an additional channel region and an additional gate region, wherein the additional channel region extends laterally and is aligned vertically with the additional gate region, wherein at least a portion of the additional channel region is arranged vertically above the field electrode region, and wherein in a vertical cross-section, the channel regions extend towards opposite sides of the field electrode trench, respectively.

7. The semiconductor die of claim 1, wherein the field electrode trench extends into a lower semiconductor body, and wherein the body region is formed in an upper epitaxial layer provided on the lower semiconductor body.

8. The semiconductor die of claim 7, wherein the upper epitaxial layer is, in a vertical cross section, interrupted by stop islands lying flush in the upper epitaxial layer.

9. The semiconductor die of claim 8, further comprising an insulating layer covering the gate electrode, wherein a Schottky contact extends through the insulating layer and contacts the drift region.

10. The semiconductor die of claim 9, wherein the Schottky contact extends through one of the stop islands.

11. The semiconductor die of claim 1, wherein the gate electrode is formed on an upper epitaxial layer, and wherein a sidewall spacer of an insulating material is formed between a sidewall of gate electrode and the epitaxial layer.

12. The semiconductor die of claim 1, further comprising a doped region formed at an end of the channel region laterally opposite to the source region, the doped region being of the same conductivity type as the source region.

13. A method of manufacturing the semiconductor die of claim 1, comprising: etching the field electrode trench; forming the field electrode region with the field electrode in the field electrode trench; forming the body region; and forming the gate region next to the body region to define the channel region.

14. The method of claim 13, wherein the body region is formed after etching the field electrode trench and after forming the field electrode region, and wherein forming the body region comprises depositing the epitaxial layer onto the frontside of the semiconductor body.

15. The method of claim 14, wherein a gate dielectric of the gate region is formed by forming a dielectric layer on the upper epitaxial layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Below, the power device and manufacturing of the same are explained in further detail by means of exemplary embodiments. Therein, the individual features can also be relevant in a different combination.

[0035] FIG. 1 shows a portion of a semiconductor die with a transistor device in a sectional view;

[0036] FIG. 2a-h illustrate some process steps for manufacturing the transistor device of FIG. 1;

[0037] FIG. 3 illustrates a further process step, which can be implemented optionally;

[0038] FIG. 4 illustrates some variants of the transistor device, which can be integrated into the die, and an additional Schottky contact;

[0039] FIG. 5 illustrates some manufacturing steps in a flow diagram.

DETAILED DESCRIPTION

[0040] FIG. 1 illustrates a transistor device 1, which has a source region 2 and a drain region 3, the latter formed at a backside. The source region 2 is arranged at a frontside, together with a body region 4, in which a channel region 4.1 is formed. A gate region 5 with a gate electrode 5.1 and a gate dielectric 5.2 is formed above the body region 4, the gate region 5 and the channel region 4.1 are oriented laterally. Between the body region 4 and the drain region 3, a drift region 6 is formed, wherein a field electrode trench 8 extends into the drift region 6. In the trench 8, a field electrode region 7 is formed, comprising a field electrode 7.1 and a field dielectric 7.2.

[0041] The field electrode trench 8 with the field electrode region 7 is formed in a lower semiconductor body 30, which can be made of a substrate, in which the drain region 3 is formed, and an epitaxial layer, in which the drift region 6 is formed. On a frontside 30.1 of the lower semiconductor body 30, an upper epitaxial layer 35 is arranged. The field electrode trench 8 extends solely in the lower semiconductor body 30, it does not reach upwards into the upper epitaxial layer 35. The trench is covered by the upper epitaxial layer 35, and the source region 2 and body region 4, as well as the gate region 5, are formed vertically above the field electrode trench 8. This allows for an efficient area use, as discussed in detail in the general description.

[0042] As apparent from the sectional view, the source region 2 is arranged vertically above the field electrode region 7, and a source contact 25 is formed centrally above the field electrode 7.1. It extends through an insulating layer 55, down to the source region 2. In this example, it contacts also the body region 4, namely extends into a highly doped body contact region 44. The latter is, like the body region 4 in the example shown here, p-doped, but with a higher doping concentration. In the example shown here, the source contact 25 ends on an insulating spacer 27 formed in the field electrode trench 8 above the field electrode region 7.

[0043] Laterally opposite to the source region 2, a doped region 70 is formed at the end of the channel region 4.1. It is of the same conductivity type as the source region 2, n-type in the example shown here, and can for instance enable a channel performance optimization.

[0044] With the source contact 2.5 arranged centrally, the channel region 4.1 and the gate region 5 extend in direction to a first side 8.1 of the field electrode trench 8. On the other side of the source contact 25, an additional body region 40 with an additional channel region 40.1 and an additional gate region 50 above are formed. They extend in direction to a second side 8.2 of the field electrode trench 8, laterally opposite to the first side 8.1. With both channel regions 4.1, 40.1 arranged above the field electrode trench 8, the area above can be used efficiently.

[0045] FIG. 2a illustrates a process step, where the field electrode trench 8 has already been etched into the lower epitaxial layer 30a formed on the substrate 30b. In the trench, the field electrode region 7 has been formed, and the trench has been filled up with the insulating spacer 27 above.

[0046] In a subsequent step shown in FIG. 2b, stop islands 36 have been formed on the lower epitaxial layer 30a, namely on the frontside 30.1 of the lower semiconductor body 30. For that purpose, a stop layer, e.g. silicon nitride layer, is deposited and structured to arrive at the islands shown in FIG. 2b. Subsequently, the upper epitaxial layer 35 is deposited epitaxially, followed by a planarization, e.g. CMP. This results in the structure shown in FIG. 2c, the stop islands 36 lying flush in the upper epitaxial layer 35.

[0047] FIGS. 2d and 2e illustrate an implantation 48 to form the body region 4 and the formation of a dielectric layer 45 for the gate dielectric, wherein the sequence of these process steps can also be inverse (layer formation prior to the implantation). Subsequently, the gate electrodes 5, 50 are formed, as shown in FIG. 2f. By a subsequent oxide or nitride deposition, combined with an etch back step, sidewall spacers 65 are thrilled at the gate electrodes 5, 50, as shown in FIG. 2g. They can protect the gate dielectric 5.2, 50.2, when the dielectric layer 45 is etched back, and prevent an implantation at the edges during subsequent implantations, e.g. for the source region.

[0048] In FIG. 2h, the insulating layer 55 has been deposited to cover the gate electrodes 5, 50, and a contact hole has been etched and filled, e.g. with tungsten, to form the source contact 25.

[0049] FIG. 3 illustrates a process step that can be implemented optionally between FIGS. 2a and 2b. Here, an upper end 27.1 of the insulating spacer 27 is recessed 39 into the field electrode trench 8, namely arranged on a smaller vertical height than the frontside 30.1 of the lower semiconductor body 30. Likewise, a portion of the body region 4 can be displaced into the field electrode trench 8, see the general description in detail.

[0050] FIG. 4 illustrates different transistor devices 1 integrated into the semiconductor die 20. In addition, between the two transistor devices 1, a Schottky contact 60 extends through the insulating layer 55, it forms a Schottky diode 60.1 with the drift region 6. The Schottky diode junction 60.1 can for instance decrease the forward voltage in diode conduction mode, see the general description in detail. The Schottky contact 60 intersects the stop island 37, allowing for an efficient area use.

[0051] The transistor device 1 shown on the right hand of the Schottky contact 60 is constructed as explained in detail with reference to FIG. 1. The transistor device 1 on the left hand of the Schottky contact 60 has basically the same set-up, differing only in the extension of the source contact 25. It extends down through the insulating spacer 27 and contacts the field electrode 7.1. Across the die 20, the two types shown can vary, wherein the impendence in a switching application can be adapted by the frequency.

[0052] On the insulating layer 55, a frontside metallization 70 is thrilled, e.g. an aluminum metallization, serving as a source metallization. The frontside metallization 70 above the cell field 71 is electrically isolated from a metallization shown on the right and serving as a gate metallization 75. Via gate contacts 76 extending through the insulating layer 55, it is electrically connected to the gate electrodes 5.1, 50.1.

[0053] FIG. 5 illustrates some process steps 80 in a flow diagram. After etching 81 the field electrode trench, the field electrode region is formed 82. For forming 83 the body region, the upper epitaxial layer is deposited and doped. By forming 84 the gate region, the channel region is defined.

[0054] Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention he limited only by the claims and the equivalents thereof.