In one example, an electronic device includes a layer of insulator on a substrate extending to a set of device elements. A first set of metal layers having a first thickness lithographically patterned and defined horizontally to the substrate on the layer of insulator. A second set of metal layers with a second thickness having a first portion defined horizontally to the substrate and patterned over and contacting the first set of metal layers, and a second portion defined vertically to the substrate and contacting the first portion and extending vertically through the layer of insulator to at least one device element and contacting the at least one device element with a width of the second thickness thereby creating at least one sub-lithographic film-edge top electrode.

A method is provided for modifying a surface of a solid conducting material, which includes applying a potential difference between this surface and a surface of another conducting solid material positioned facing it, and wherein, simultaneously, the surface (S) is put into contact with a liquid medium comprising in solution triarylamines (I): ##STR00001##
while subjecting these triarylamines (I) to electromagnetic radiation, at least partly converting them at into triarylammonium radicals. Also provided is a conducting device which includes two conducting metal materials, the surfaces of which, (S) and (S′) respectively, are electrically interconnected through an organic material comprising conducting fibrillar organic supramolecular species comprising an association of triarylamines of formula (I).

A metal-insulator-metal (MIM) capacitor includes a bottom electrode cup, an insulator, and a top electrode. The bottom electrode cup includes a laterally-extending bottom electrode cup base and a bottom electrode cup sidewall extending upwardly from the laterally-extending bottom electrode cup base. The insulator includes an insulator cup formed in an opening defined by the bottom electrode cup, and a rounded insulator flange extending laterally outwardly and curving upwardly from the insulator cup, the rounded insulator flange covering an upper surface of the bottom electrode cup sidewall. The top electrode is formed in an opening defined by the insulator cup. The top electrode is insulated from the upper surface of the bottom electrode cup sidewall by the rounded insulator flange.

In some embodiments, the present disclosure relates to an integrated chip having an inter-tier interconnecting structure having horizontal components, which is arranged within a semiconductor substrate and configured to electrically couple a first device tier to a second device tier. The integrated chip has a first device tier with a first semiconductor substrate. A first inter-tier interconnecting structure is disposed inside the first semiconductor substrate. The first inter-tier interconnecting structure has a first segment extending in a first direction and a second segment protruding outward from a sidewall of the first segment in a second direction substantially perpendicular to the first direction. A second device tier is electrically coupled to the first device tier by the first inter-tier interconnecting structure.

A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

Interconnect structures that maximize integrated circuit (IC) density and corresponding formation techniques are disclosed. An exemplary IC device includes a gate layer extending along a first direction. An interconnect structure disposed over the gate layer includes odd-numbered interconnect routing layers oriented along a second direction that is substantially perpendicular to the first direction and even-numbered interconnect routing layers oriented along a third direction that is substantially parallel to the first direction. In some implementations, a ratio of a gate pitch of the gate layer to a pitch of a first of the even-numbered interconnect routing layers to a pitch of a third of the even-numbered interconnect routing layers is 3:2:4. In some implementations, a pitch of a first of the odd-numbered interconnect routing layers to a pitch of a third of the odd-numbered interconnect routing layers to a pitch of a seventh of the odd-numbered interconnect routing layers is 1:1:2.

A flexible display and method of manufacturing the same are disclosed. In one aspect, the display includes a flexible substrate having a bending area and a non-bending area and a plurality of metal wirings formed over the flexible substrate in the bending area and the non-bending area. Each of the metal wirings which are formed in the bending area includes a pair of first hard wirings formed over the flexible substrate and a first soft wiring electrically connected to ends of the pair of first hard wirings.

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

The present disclosure relates to a method of forming a BEOL metallization layer that uses different conductive materials (e.g., metals) to fill different size openings in an inter-level dielectric layer, and an associated apparatus. In some embodiments, the present disclosure relates to an integrated chip having a first plurality of metal interconnect structures disposed within a first BEOL metallization layer, which include a first conductive material. The integrated chip also has a second plurality of metal interconnect structures disposed within the first BEOL metallization layer at positions laterally separated from the first plurality of metal interconnect structures. The second plurality of metal interconnect structures have a second conductive material that is different than the first conductive material. By forming different metal interconnect structures on a same BEOL metallization layer using different conductive materials, gap-fill problems in narrow BEOL metal interconnect structures can be mitigated, thereby improving reliability of integrated chips.

Disclosed is a method of designing and fabricating a semiconductor chip including a fuse cell. The method may include preparing a semiconductor chip layout, the semiconductor chip layout including a main chip layout and a scribe lane layout enclosing the main chip layout; disposing a fuse layout in the scribe lane layout; setting the main chip layout as a first data preparation region; setting the scribe lane layout and the fuse layout as a second data preparation region; obtaining a first resulting structure and a second resulting structure, respectively, by performing a data preparation process on the first and second data preparation regions; merging the first and second resulting structures to generate mask data; manufacturing a photomask, based on the mask data; and forming semiconductor chips on a wafer using the photomask.