A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region and a drain region. A sacrificial spacer may be formed on a sidewall of the trench and on a sidewall of the gate structure. A metal contact may then be formed in the trench to at least one of the source region and the drain region. The metal contact has a base width that is less than an upper surface width of the metal contact. The sacrificial spacer may be removed, and a substantially conformal dielectric material layer can be formed on sidewalls of the metal contact and the gate structure. Portions of the conformally dielectric material layer contact one another at a pinch off region to form an air gap between the metal contact and the gate structure.

A method includes forming a gate structure and an interlayer dielectric (ILD) layer over a substrate; selectively forming an inhibitor over the gate structure; performing an atomic layer deposition (ALD) process to form a dielectric layer over the ILD layer, wherein in the ALD process the dielectric layer has greater growing rate on the ILD than on the inhibitor; and performing an atomic layer etching (ALE) process to etch the dielectric layer until a top surface of the inhibitor is exposed, in which a portion of the dielectric layer remains on the ILD layer after the ALE process is complete.

A method of manufacturing a FinFET includes at last the following steps. A semiconductor substrate is patterned to form trenches in the semiconductor substrate and semiconductor fins located between two adjacent trenches of the trenches. Gate stacks is formed over portions of the semiconductor fins. Strained material portions are formed over the semiconductor fins revealed by the gate stacks. First metal contacts are formed over the gate stacks, the first metal contacts electrically connecting the strained material portions. Air gaps are formed in the FinFET at positions between two adjacent gate stacks and between two adjacent strained materials.

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes forming a bit line on a substrate, forming a first dielectric layer over the substrate and surrounding a lower portion of the bit line, forming a second dielectric layer over the bit line and the first dielectric layer, forming a contact over the second dielectric layer, wherein a height of the contact above the substrate is greater than a height of the first dielectric layer above the substrate, removing the first dielectric layer and the second dielectric layer, and forming a third dielectric layer conformally over the bit line, the substrate and the contact, thereby forming an air gap between the contact and the bit line.

A method for etching a metal containing feature is provided. Using a pattern mask, layers of material are etched to expose a portion of a metal containing feature. At least a portion of the exposed metal containing feature is etched, and is replaced by the growth of a filler dielectric. The etched portion of the metal containing feature and the filler dielectric reduce the unwanted conductivity between adjacent metal containing features.

A semiconductor device includes a first stack structure including first interlayer insulating layers and first conductive patterns alternately stacked on each other in a first direction and a second conductive pattern comprising electrode portions and a connecting portion. The electrode portions of the second conductive pattern are stacked to be spaced apart from each other above the first stack structure. The connecting portion of the second conductive pattern extends in the first direction to intersect the electrode portions and couples the electrode portions. The semiconductor device further includes a vertical channel and a vertical conductive structure that pass through the first stack structure and the electrode portions of the second conductive pattern. The vertical conductive structure is spaced apart from the first stack structure and the second conductive pattern.

Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

A semiconductor device including a fin field effect transistor (fin-FET) includes active fins disposed on a substrate, isolation layers on both sides of the active fins, a gate structure formed to cross the active fins and the isolation layers, source/drain regions on the active fins on sidewalls of the gate structure, a first interlayer insulating layer on the isolation layers in contact with portions of the sidewalls of the gate structure and portions of surfaces of the source/drain regions, an etch stop layer configured to overlap the first interlayer insulating layer, the sidewalls of the gate structure, and the source/drain regions, and contact plugs formed to pass through the etch stop layer to contact the source/drain regions. The source/drain regions have main growth portions in contact with upper surfaces of the active fins.

Source/drain contacts between transistor gates with abbreviated inner spacers for improved contact area are disclosed. Related methods of fabricating source/drain contacts and abbreviated inner spacers are also disclosed. Inner spacers formed on sidewalls of the gates of adjacent transistors are abbreviated to reduce an amount of the space the inner spacers occupy on the source/drain region, increasing a critical dimension of the source/drain contact. Abbreviated inner spacers extend from a top of the gate over a portion of the sidewalls to provide leakage current protection but do not fully extend to the semiconductor substrate. As a result, the critical dimension of the source/drain contact can extend from a sidewall on a first gate to a sidewall on a second gate. A source/drain contact formed between gates with abbreviated inner spacers has a greater surface area in contact with the source/drain region providing decreased contact resistance.

The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.