A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a support substrate fixing step of fixing the wafer to a support substrate, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region, and fixing the device chip to the support substrate.

A wafer manufacturing method includes a wafer preparing step of preparing a wafer including a semiconductor device formed in each of a plurality of regions demarcated by a plurality of streets intersecting each other, a removing step of removing, from the wafer, a defective device region including a semiconductor device determined to be a defective product among a plurality of the semiconductor devices formed in the wafer, and a fitting step of fitting, into a removed region formed by removing the defective device region from the wafer, a device chip including a semiconductor device as a non-defective product having same functions as those of the semiconductor device determined to be a defective product and having a size capable of being fitted into the removed region.

A method of forming a semiconductor device includes: forming an etch stop layer over a substrate; forming a first diffusion barrier layer over the etch stop layer; forming a semiconductor device layer over the first diffusion barrier layer, the semiconductor device layer including a transistor; forming a first interconnect structure over the semiconductor device layer at a front side of the semiconductor device layer, the first interconnect structure electrically coupled to the transistor; attaching the first interconnect structure to a carrier; removing the substrate, the etch stop layer, and the first diffusion barrier layer after the attaching; and forming a second interconnect structure at a backside of the semiconductor device layer after the removing.

A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).

A method for fabricating a semiconductor device includes: providing a first wafer including a base substrate having a first surface and a second surface facing each other, and an element region disposed on the first surface of the base substrate, in which the first wafer includes a first semiconductor chip region and a second semiconductor chip region adjacent to each other, each including a portion of the base substrate and a portion of the element region; forming a cutting pattern in the base substrate between the first semiconductor chip region and the second semiconductor chip region; grinding a part of the base substrate to form a second wafer from the first wafer; forming a stress relief layer on the second surface of the ground base substrate; and expanding the second wafer to separate the first semiconductor chip region and the second semiconductor chip region from each other.

The invention relates to a method for producing at least one optoelectronic component (100) comprising the steps A) providing an auxiliary carrier (1), B) epitaxially applying a sacrificial layer (2) on the auxiliary carrier (1), wherein the sacrificial layer (2) comprises germanium, C) epitaxially applying a semiconductor layer sequence (3) on the sacrificial layer (2), D) removing the sacrificial layer (2) by means of dry etching (9), such that the auxiliary carrier (1) is removed from the semiconductor layer sequence (3).

A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate. Drain electrode contacts are formed over the semiconductor region while gate electrode and source electrode contacts are formed by etching portions of a metallic layer formed over the first side of the substrate.

Methods, systems, and devices for double side back-end-of-line (BEOL) metallization for pseudo through-silicon via (pTSV) integration are described. An integrated circuit (IC) may include multiple metallic layers integrated within multiple layers of a multi-dimensional integrated stack (e.g., a three dimensional (3D) integrated stack). By performing a BEOL metallization process, the integrated circuit may implement techniques for 3D vertical chip integration. For example, a first set of layers may be formed during a first portion of a BEOL process and a second portion of the BEOL process may integrate a second set of metallic layers as well as a buried power delivery network (PDN). The metallic layers may form a number of pTSVs and may promote a PDN to experience a reduced PDN IR drop. The PDN may be integrated and the pTSVs may be formed by integrating the metallic layers within a number of dielectric layers.

A semiconductor device, the device including: a first level overlaid by a first memory level, where the first memory level includes a first thinned single crystal substrate; a second memory level, the second memory level disposed on top of the first memory level, where the second memory level includes a second thinned single crystal substrate; and a memory control level disposed on top of the second memory level, where the memory control level is bonded to the second memory level, and where the bonded includes oxide to oxide and conductor to conductor bonding.

A method for transferring a superficial layer from a detachable structure comprises the following steps: a) supplying the detachable structure comprising: •a support substrate, •a detachable layer arranged on the support substrate along a main plane and comprising a plurality of walls that are separated from one another, each wall having at least one side that is perpendicular to the main plane; •a superficial layer arranged on the detachable layer along the main plane; b) applying a mechanical force configured to cause said walls to bend, along a direction that is secant to said side, until causing the mechanical rupture of the walls, in order to detach the superficial layer from the support substrate.