Disclosed are a film touch sensor in which a separation layer is formed on a carrier substrate prior to the formation procedures of the touch sensor and an insulation layer is formed to be used as a planarization layer, an adhesive layer or a base layer, and a method of preparing the film touch sensor.

A method of splitting a semiconductor work piece includes: forming a separation zone within the semiconductor work piece, wherein forming the separation zone comprises modifying semiconductor material of the semiconductor work piece at a plurality of targeted positions within the separation zone in at least one physical property which increases thermo-mechanical stress within the separation zone relative to a remainder of the semiconductor work piece, wherein modifying the semiconductor material in one of the targeted positions comprises focusing at least two laser beams to the targeted position; and applying an external force or stress to the semiconductor work piece such that at least one crack propagates along the separation zone and the semiconductor work piece splits into two separate pieces. Additional work piece splitting techniques and techniques for compensating work piece deformation that occurs during the splitting process are also described.

A device includes a first laser emitter, a second laser emitter, and a separating portion. The first laser emitter is configured to emit, in an outer circumferential portion of a bonded substrate including a first substrate and a second substrate bonded to each other, a first laser beam into the first substrate from a side of the first substrate to form a modified layer. The second laser emitter is configured to emit a second laser beam to a material layer that is arranged between the first substrate and the second substrate and is provided on the second substrate from a side of the second substrate, to cause peeling between the second substrate and the material layer. The separating portion is configured to separate an outer circumferential portion of the first substrate and an outer circumferential portion of the material layer from the outer circumferential portion of the bonded substrate.

A method of fabricating an electronic device can include forming a plurality of vertical channels having sidewalls over a substrate, and forming gate dielectric regions over portions of the vertical channels and planar regions adjoining the vertical channels. Gate electrode regions are then formed over portions of the gate dielectric regions. The gate electrode material and the vertical channel region are doped and sized to enable full depletion of charges during operation. Source and body tie regions are formed on the vertical sidewalls by doping with a p-type or n-type dopant. Dielectric regions over the gate electrode regions are formed to electrically isolate the gate electrode regions from the source regions. A metallic layer is formed over the first side of the substrate having the vertical channels. Stress is then induced within the substrate by annealing and/or cooling to separate a semiconductor region of the substrate and the metallic layer from the remaining portion of the substrate. Drain electrode contacts are formed over the semiconductor region while gate electrode and source electrode contacts are formed by etching portions of a metallic layer formed over the first side of the substrate.

A method for manufacturing an optical device includes providing a carrier waver, provide a first substrate having a first surface region, and forming a first gallium and nitrogen containing epitaxial material overlying the first surface region. The first epitaxial material includes a first release material overlying the first substrate. The method also includes patterning the first epitaxial material to form a plurality of first dice arranged in an array; forming a first interface region overlying the first epitaxial material; bonding the first interface region of at least a fraction of the plurality of first dice to the carrier wafer to form bonded structures; releasing the bonded structures to transfer a first plurality of dice to the carrier wafer, the first plurality of dice transferred to the carrier wafer forming mesa regions on the carrier wafer; and forming an optical waveguide in each of the mesa regions, the optical waveguide configured as a cavity to form a laser diode of the electromagnetic radiation.

A nitride semiconductor device includes: a diamond substrate; a first graphene layer provided on the diamond substrate; a second graphene layer provided on the first graphene layer; a nitride semiconductor layer provided on the second graphene layer; and a nitride semiconductor element having an electrode provided on the nitride semiconductor layer, wherein the first and second graphene layers are provided as an interface layer between the diamond substrate and the nitride semiconductor layer.

A semiconductor device includes a diamond substrate made of diamond, and a nitride semiconductor layer formed in a recess formed at an upper surface of the diamond substrate. The semiconductor device further includes at least one of: (A) the nitride semiconductor layer formed to be surrounded entirely by the upper surface of the diamond substrate in a plan view; (B) the diamond substrate in which the upper surface of the diamond substrate and an upper surface of the nitride semiconductor layer are located on the same plane; and (C) the diamond substrate having electrical insulating properties.

The present invention includes: transferring a C-plane sapphire thin film 1t having an off-angle of 0.5-5° onto a handle substrate composed of a ceramic material having a coefficient of thermal expansion at 800 K that is greater than that of silicon and less than that of C-plane sapphire; performing high-temperature nitriding treatment on the GaN epitaxial growth substrate 11 and covering the surface of the C-plane sapphire thin film 1t with a surface treatment layer 11a made of AlN; having GaN grow epitaxially on the surface treatment layer 11a; ion-implanting a GaN film 13; pasting and bonding together the GaN film-side surface of the ion-implanted GaN film carrier and a support substrate 12; performing peeling at an ion implantation region 13.sub.ion in the GaN film 13 and transferring a GaN thin film 13a onto the support substrate 12; and obtaining a GaN laminate substrate 10.

A self-aligned short-channel SASC electronic device includes a first semiconductor layer formed on a substrate; a first metal layer formed on a first portion of the first semiconductor layer; a first dielectric layer formed on the first metal layer and extended with a dielectric extension on a second portion of the first semiconductor layer that extends from the first portion of the first semiconductor layer, the dielectric extension defining a channel length of a channel in the first semiconductor layer; and a gate electrode formed on the substrate and capacitively coupled with the channel. The dielectric extension is conformally grown on the first semiconductor layer in a self-aligned manner. The channel length is less than about 800 nm, preferably, less than about 200 nm, more preferably, about 135 nm.

A semiconductor device includes an active region and a trapping region positioned peripherally with respect to the active region, the trapping region presenting trapping apertures permitting the passage of particles, the trapping apertures being in fluid communication with at least one trapping chamber for trapping the particles. A method for manufacturing the semiconductor devices from one semiconductor wafer presents semiconductor device regions to be singulated along a dicing portion line. The method includes in each semiconductor device region, making a semiconductor device precursor by making or applying at least one active element in an active region, making at least one trapping chamber and making, in a trapping region of the semiconductor device region positioned more peripherally than the active region, trapping apertures in fluid communication with the at least one trapping chamber; and singulating the semiconductor device regions by separating the semiconductor device precursors along the dicing portion lines.